mirror of https://github.com/llvm/circt.git
104 lines
2.7 KiB
Plaintext
104 lines
2.7 KiB
Plaintext
; RUN: firtool --split-input-file --verify-diagnostics %s
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; Tests extracted from:
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; - test/scala/firrtlTests/WidthSpec.scala
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; Dshl by more than 31 bits should result in an error
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FIRRTL version 4.0.0
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circuit Unit :
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public module Unit :
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input x : UInt<3>
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input y : UInt<32>
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; expected-error @+1 {{shift amount too large: second operand of dshl is wider than 31 bits}}
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node z = dshl(x, y)
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// -----
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; Dshl by to more than 31 bits total width should result in an error
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FIRRTL version 4.0.0
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circuit Unit :
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public module Unit :
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input x : UInt<1073741825>
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input y : UInt<30>
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; expected-error @+1 {{shift amount too large: first operand shifted by maximum amount exceeds maximum width}}
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node z = dshl(x, y)
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// -----
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; Casting a multi-bit signal to Clock should result in error
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FIRRTL version 4.0.0
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circuit Unit :
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public module Unit :
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input i: UInt<2>
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; expected-error @+1 {{must be 1-bit uint/sint/analog, reset, asyncreset, or clock}}
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node x = asClock(i)
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// -----
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; Casting a multi-bit signal to AsyncReset should result in error
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FIRRTL version 4.0.0
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circuit Unit :
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public module Unit :
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input i: UInt<2>
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; expected-error @+1 {{operand must be single bit scalar type}}
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node x = asAsyncReset(i)
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// -----
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; Width >= MaxWidth should result in an error
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FIRRTL version 4.0.0
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circuit Unit :
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public module Unit :
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; expected-error @+1 {{value is too big to handle}}
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input x: UInt<2147483648>
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// -----
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; Circular reg depending on reg + 1 should error
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FIRRTL version 4.0.0
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circuit Unit :
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public module Unit :
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input clock: Clock
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input reset: UInt<1>
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; expected-error @+1 {{'firrtl.regreset' op is constrained to be wider than itself}}
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regreset r : UInt, clock, reset, UInt(3)
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; expected-note @+1 {{constrained width W >= W+1 here:}}
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node T_7 = add(r, r)
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; expected-note @+1 {{constrained width W >= W+1 here:}}
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connect r, T_7
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// -----
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; Add of UInt<2> and SInt<2> should error
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FIRRTL version 4.0.0
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circuit Unit :
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public module Unit :
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input x: UInt<2>
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input y: SInt<2>
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; expected-error @+1 {{operand signedness must match}}
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node z = add(x, y)
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// -----
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; SInt<2> - UInt<3> should error
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FIRRTL version 4.0.0
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circuit Unit :
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public module Unit :
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input x: UInt<3>
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input y: SInt<2>
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; expected-error @+1 {{operand signedness must match}}
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node z = sub(y, x)
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// -----
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; Should provide a good error message with a full target if a user forgets an
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; assign.
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FIRRTL version 4.0.0
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circuit Foo :
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public module Foo :
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input clock : Clock
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inst bar of Bar
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module Bar :
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; expected-error @+1 {{uninferred width: wire "a.c.e" is unconstrained}}
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wire a: { b : UInt<1>, c : { d : UInt<1>, e : UInt } }
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invalidate a
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