mirror of https://github.com/llvm/circt.git
47 lines
2.4 KiB
MLIR
47 lines
2.4 KiB
MLIR
// RUN: firtool --verilog %s | FileCheck %s
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firrtl.circuit "Foo" {
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firrtl.extmodule @Bar(
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in extClockIn: !firrtl.clock sym @symExtClockIn,
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out extClockOut: !firrtl.clock sym @symExtClockOut
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)
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firrtl.module @Foo(
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in %value: !firrtl.uint<42> sym @symValue,
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in %clock: !firrtl.clock sym @symClock,
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in %reset: !firrtl.uint<1> sym @symReset
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) {
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%instName_clockIn, %instName_clockOut = firrtl.instance instName sym @instSym @Bar(in extClockIn: !firrtl.clock, out extClockOut: !firrtl.clock)
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%nodeName = firrtl.node sym @nodeSym %value : !firrtl.uint<42>
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%wireName = firrtl.wire sym @wireSym : !firrtl.uint<42>
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%regName = firrtl.reg sym @regSym %clock : !firrtl.clock, !firrtl.uint<42>
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%regResetName = firrtl.regreset sym @regResetSym %clock, %reset, %value : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<42>, !firrtl.uint<42>
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%invalid_ui42 = firrtl.invalidvalue : !firrtl.uint<42>
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firrtl.connect %instName_clockIn, %clock : !firrtl.clock, !firrtl.clock
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firrtl.connect %wireName, %invalid_ui42 : !firrtl.uint<42>, !firrtl.uint<42>
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}
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}
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// CHECK: ----- 8< -----
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sv.verbatim "----- 8< -----"
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sv.verbatim "VERB symExtClockIn = `{{0}}`" {symbols = [#hw.innerNameRef<@Bar::@symExtClockIn>]}
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sv.verbatim "VERB symExtClockOut = `{{0}}`" {symbols = [#hw.innerNameRef<@Bar::@symExtClockOut>]}
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// CHECK-NEXT: VERB symExtClockIn = `extClockIn`
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// CHECK-NEXT: VERB symExtClockOut = `extClockOut`
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sv.verbatim "VERB symValue = `{{0}}`" {symbols = [#hw.innerNameRef<@Foo::@symValue>]}
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sv.verbatim "VERB symClock = `{{0}}`" {symbols = [#hw.innerNameRef<@Foo::@symClock>]}
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sv.verbatim "VERB symReset = `{{0}}`" {symbols = [#hw.innerNameRef<@Foo::@symReset>]}
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// CHECK-NEXT: VERB symValue = `value`
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// CHECK-NEXT: VERB symClock = `clock`
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// CHECK-NEXT: VERB symReset = `reset`
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sv.verbatim "VERB instSym = `{{0}}`" {symbols = [#hw.innerNameRef<@Foo::@instSym>]}
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sv.verbatim "VERB nodeSym = `{{0}}`" {symbols = [#hw.innerNameRef<@Foo::@nodeSym>]}
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sv.verbatim "VERB wireSym = `{{0}}`" {symbols = [#hw.innerNameRef<@Foo::@wireSym>]}
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sv.verbatim "VERB regSym = `{{0}}`" {symbols = [#hw.innerNameRef<@Foo::@regSym>]}
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sv.verbatim "VERB regResetSym = `{{0}}`" {symbols = [#hw.innerNameRef<@Foo::@regResetSym>]}
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// CHECK-NEXT: VERB instSym = `instName`
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// CHECK-NEXT: VERB nodeSym = `nodeName`
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// CHECK-NEXT: VERB wireSym = `wireName`
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// CHECK-NEXT: VERB regSym = `regName`
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// CHECK-NEXT: VERB regResetSym = `regResetName`
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