mirror of https://github.com/llvm/circt.git
67 lines
2.0 KiB
Plaintext
67 lines
2.0 KiB
Plaintext
; RUN: firtool --verilog --allow-adding-ports-on-public-modules %s | FileCheck %s
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FIRRTL version 4.0.0
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circuit Top : %[[
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{
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"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
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"target":"~Top|DUTModule"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~Top|Top>memTap"
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},
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{"class": "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"},
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{
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"class":"sifive.enterprise.grandcentral.MemTapAnnotation",
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"source":"~Top|DUTModule>rf",
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"sink":[
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"~Top|Top>memTap[0]",
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"~Top|Top>memTap[1]",
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"~Top|Top>memTap[2]",
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"~Top|Top>memTap[3]",
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"~Top|Top>memTap[4]",
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"~Top|Top>memTap[5]",
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"~Top|Top>memTap[6]",
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"~Top|Top>memTap[7]"
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]
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}
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]]
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module DUTModule :
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input clock : Clock
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input reset : Reset
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output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}
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cmem rf : UInt<8> [8]
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infer mport read = rf[io.addr], clock
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connect io.dataOut, read
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when io.wen :
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infer mport write = rf[io.addr], clock
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connect write, io.dataIn
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public module Top :
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input clock : Clock
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input reset : UInt<1>
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output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}
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inst dut of DUTModule
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connect dut.clock, clock
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connect dut.reset, reset
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wire memTap : UInt<8>[8]
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invalidate memTap
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connect io.dataOut, dut.io.dataOut
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connect dut.io.wen, io.wen
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connect dut.io.dataIn, io.dataIn
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connect dut.io.addr, io.addr
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; CHECK: module Top(
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; CHECK-NOT: module
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; CHECK: wire [7:0] memTap_0 = Top.dut.rf_0_probe;
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; CHECK-NEXT: wire [7:0] memTap_1 = Top.dut.rf_1_probe;
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; CHECK-NEXT: wire [7:0] memTap_2 = Top.dut.rf_2_probe;
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; CHECK-NEXT: wire [7:0] memTap_3 = Top.dut.rf_3_probe;
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; CHECK-NEXT: wire [7:0] memTap_4 = Top.dut.rf_4_probe;
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; CHECK-NEXT: wire [7:0] memTap_5 = Top.dut.rf_5_probe;
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; CHECK-NEXT: wire [7:0] memTap_6 = Top.dut.rf_6_probe;
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; CHECK-NEXT: wire [7:0] memTap_7 = Top.dut.rf_7_probe;
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; CHECK: endmodule
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