mirror of https://github.com/llvm/circt.git
82 lines
2.3 KiB
Plaintext
82 lines
2.3 KiB
Plaintext
; RUN: firtool --parse-only --split-input-file %s | FileCheck %s
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; RUN: firtool --verilog --split-input-file %s
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; RUN: firtool --parse-only --lower-annotations-no-ref-type-ports --split-input-file %s | FileCheck %s --check-prefixes NOREF --implicit-check-not firrtl.ref
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; RUN: firtool --verilog --lower-annotations-no-ref-type-ports --split-input-file %s
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; Test tapping a bundle with flips, tap sink is passive.
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; CHECK-LABEL: module private @Child(
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; CHECK: firrtl.ref.send
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; CHECK-SAME: !firrtl.bundle<a: uint<2>, b flip: uint<2>>
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; CHECK-LABEL: module @Top(
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; CHECK: firrtl.ref.resolve
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; CHECK-SAME: !firrtl.probe<bundle<a: uint<2>, b: uint<2>>>
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; NOREF-LABEL: module private @Child(
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; NOREF-SAME: out %[[OUT_PORT:.+]]: !firrtl.bundle<a: uint<2>, b: uint<2>>
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; NOREF-DAG: %[[A:.+]] = firrtl.subfield %[[OUT_PORT]][a]
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; NOREF-DAG: firrtl.matchingconnect %[[A]],
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; NOREF-DAG: %[[B:.+]] = firrtl.subfield %[[OUT_PORT]][b]
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; NOREF-DAG: firrtl.matchingconnect %[[B]],
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FIRRTL version 4.0.0
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circuit Top : %[[
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{
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"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
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"keys": [
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{
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"class": "sifive.enterprise.grandcentral.ReferenceDataTapKey",
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"source": "~Top|Top/c:Child>x",
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"sink": "~Top|Top>sink"
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}
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]
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}
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]]
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module Child :
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input x: {a : UInt<2>, flip b: UInt<2>}
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connect x.b, UInt<2>(2)
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public module Top :
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input x: {a : UInt<2>, flip b: UInt<2>}
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output tap : {a : UInt<2>, b: UInt<2>}
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inst c of Child
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connect c.x, x
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wire sink : {a : UInt<2>, b: UInt<2>}
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connect tap, sink
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; // -----
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; Check same but where no ports are inserted.
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; CHECK-LABEL: circuit "Local"
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; NOREF-LABEL: circuit "Local"
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FIRRTL version 4.0.0
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circuit Local: %[[
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{
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"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
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"keys": [
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{
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"class": "sifive.enterprise.grandcentral.ReferenceDataTapKey",
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"source": "~Local|Local>x",
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"sink": "~Local|Local>sink"
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},
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{
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"class": "sifive.enterprise.grandcentral.ReferenceDataTapKey",
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"source": "~Local|Local>x",
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"sink": "~Local|Local>unused_sink"
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}
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]
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}
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]]
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public module Local:
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input x: {a : UInt<2>, flip b: UInt<2>}
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output tap : {a : UInt<2>, b: UInt<2>}
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connect x.b, x.a
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wire sink : {a : UInt<2>, b: UInt<2>}
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connect tap, sink
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wire unused_sink : {a : UInt<2>, b: UInt<2>}
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