mirror of https://github.com/llvm/circt.git
69 lines
1.9 KiB
Plaintext
69 lines
1.9 KiB
Plaintext
; RUN: firtool --split-input-file --verilog %s | FileCheck %s
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; Tests extracted from:
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; - test/scala/firrtlTests/AsyncResetSpec.scala
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; Unclear if we want to require this split of processes in MFC.
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; XFAIL: *
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; Every async reset reg should generate its own always block.
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; CHECK-LABEL: module Foo(
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FIRRTL version 4.0.0
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circuit Foo:
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public module Foo:
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input clock0 : Clock
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input clock1 : Clock
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input syncReset : UInt<1>
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input asyncReset : AsyncReset
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input x : UInt<8>[5]
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output z : UInt<8>[5]
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regreset r0 : UInt<8>, clock0, syncReset, UInt(123)
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regreset r1 : UInt<8>, clock1, syncReset, UInt(123)
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regreset r2 : UInt<8>, clock0, asyncReset, UInt(123)
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regreset r3 : UInt<8>, clock0, asyncReset, UInt(123)
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regreset r4 : UInt<8>, clock1, asyncReset, UInt(123)
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connect r0, x[0]
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connect r1, x[1]
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connect r2, x[2]
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connect r3, x[3]
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connect r4, x[4]
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connect z[0], r0
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connect z[1], r1
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connect z[2], r2
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connect z[3], r3
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connect z[4], r4
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; CHECK: always @(posedge clock0) begin
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; CHECK: if (syncReset)
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; CHECK: r0 <= 8'h7B;
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; CHECK: else
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; CHECK: r0 <= x_0;
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; CHECK: end
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; CHECK: always @(posedge clock1) begin
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; CHECK: if (syncReset)
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; CHECK: r1 <= 8'h7B;
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; CHECK: else
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; CHECK: r1 <= x_1;
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; CHECK: end
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; CHECK: always @(posedge clock0 or posedge asyncReset) begin
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; CHECK: if (asyncReset)
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; CHECK: r2 <= 8'h7B;
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; CHECK: else
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; CHECK: r2 <= x_2;
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; CHECK: end
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; CHECK: always @(posedge clock0 or posedge asyncReset) begin
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; CHECK: if (asyncReset)
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; CHECK: r3 <= 8'h7B;
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; CHECK: else
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; CHECK: r3 <= x_3;
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; CHECK: end
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; CHECK: always @(posedge clock1 or posedge asyncReset) begin
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; CHECK: if (asyncReset)
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; CHECK: r4 <= 8'h7B;
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; CHECK: else
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; CHECK: r4 <= x_4;
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; CHECK: end
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