mirror of https://github.com/llvm/circt.git
71 lines
1.9 KiB
Plaintext
71 lines
1.9 KiB
Plaintext
; RUN: firtool %s | FileCheck %s
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FIRRTL version 4.0.0
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circuit PortDelete : %[[
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{
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"class": "sifive.enterprise.grandcentral.GrandCentralView$SerializedViewAnnotation",
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"name": "MyView",
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"companion": "~PortDelete|MyView_companion",
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"parent": "~PortDelete|DUT",
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"view": {
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"class": "sifive.enterprise.grandcentral.AugmentedBundleType",
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"defName": "MyInterface",
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"elements": [
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{
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"name": "ground",
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"description": "a ground type port",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "PortDelete",
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"module": "PortDelete",
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"path": [
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{
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"_1": {
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"class": "firrtl.annotations.TargetToken$Instance",
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"value": "dut"
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},
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"_2": {
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"class": "firrtl.annotations.TargetToken$OfModule",
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"value": "DUT"
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}
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}
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],
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"ref": "w",
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"component": []
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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}
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]
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}
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}
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]]
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module MyView_companion :
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wire _WIRE : UInt<1>
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connect _WIRE, UInt<1>(0h0)
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module DUT :
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output out : UInt<1>
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wire w : UInt<1>
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connect w, UInt<1>(0h1)
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connect out, w
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inst MyView_companion of MyView_companion
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public module PortDelete :
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output out : UInt<1>
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inst dut of DUT
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connect out, dut.out
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; Assert that the DUT has no ports in Verilog. This ensures that even though
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; wire "w" is part of a Grand Central View, it does not block optimizations.
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; The constant one is allowed to flow through w and out of the design which
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; makes the output port "out" on the DUT capable of being deleted.
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;
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; CHECK-LABEL: module DUT();
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