mirror of https://github.com/llvm/circt.git
51 lines
1.1 KiB
Plaintext
51 lines
1.1 KiB
Plaintext
; RUN: firtool --annotation-file %S/HWRename.anno.json %s | FileCheck %s
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FIRRTL version 4.0.0
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circuit Top:
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module Companion :
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output io : { }
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wire _WIRE : UInt<1>
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connect _WIRE, UInt<1>(0h0)
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module DUT:
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input a: UInt<1>
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output b: UInt<1>
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wire signed: UInt<1>
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connect signed, a
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connect b, signed
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inst companion of Companion
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public module Top:
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input a: UInt<1>
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output b: UInt<1>
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inst signed of DUT
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connect signed.a, a
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connect b, signed.b
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; CHECK: module Companion(
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; CHECK: input [[port:[a-zA-Z0-9_]+]]
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; CHECK: );
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; CHECK: MyInterface MyView();
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; CHECK-NEXT: assign MyView.[[elementName:.+]] = [[port]];
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; CHECK-NEXT: endmodule
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; CHECK: module DUT
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; CHECK: input a
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; CHECK: Companion companion (
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; CHECK-NEXT: .[[port]] (a)
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; CHECK-NEXT: );
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; CHECK: endmodule
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; CHECK: module Top
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; CHECK: DUT [[dutName:.+]] (
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; CHECK: endmodule
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; CHECK: interface MyInterface
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; CHECK-NEXT: logic [[elementName]]
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; CHECK-NEXT: endinterface
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