mirror of https://github.com/llvm/circt.git
25 lines
1.1 KiB
MLIR
25 lines
1.1 KiB
MLIR
// RUN: circt-translate --export-calyx --split-input-file --verify-diagnostics %s | FileCheck %s --strict-whitespace
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module attributes {calyx.entrypoint = "main"} {
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// CHECK: import "primitives/memories/seq.futil";
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// CHECK-LABEL: component main<"static"=1,>(in: 32, @go go: 1, @clk clk: 1, @reset reset: 1) -> (out: 32, @done done: 1) {
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calyx.component @main(%in: i32, %go: i1 {go}, %clk: i1 {clk}, %reset: i1 {reset}) -> (%out: i32, %done: i1 {done}) {
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%c1_1 = hw.constant 1 : i1
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%m1.addr0, %m1.clk, %m1.reset, %m1.content_en, %m1.write_en, %m1.write_data, %m1.read_data, %m1.done = calyx.seq_mem @m1 <[64] x 32> [6] : i6, i1, i1, i1, i1, i32, i32, i1
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calyx.wires {
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// CHECK: done = m1.done
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calyx.assign %done = %m1.done : i1
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// CHECK: m1.write_en = go
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calyx.assign %m1.write_en = %go : i1
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// CHECK: m1.content_en = go
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calyx.assign %m1.content_en = %go : i1
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// CHECK: m1.write_data = in
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calyx.assign %m1.write_data = %in : i32
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// CHECK: out = m1.read_data
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calyx.assign %out = %m1.read_data : i32
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}
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calyx.control {}
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} {static = 1}
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}
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