mirror of https://github.com/llvm/circt.git
25 lines
1.4 KiB
MLIR
25 lines
1.4 KiB
MLIR
// RUN: circt-opt --lower-pipeline-to-hw="clock-gate-regs" %s | FileCheck %s
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// CHECK: hw.module @testSingle(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[VAL_2:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_4:.*]] : i1, out out0 : i32, out out1 : i1) {
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// CHECK: %[[VAL_5:.*]] = comb.sub %[[VAL_0]], %[[VAL_1]] : i32
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// CHECK: %[[VAL_6:.*]] = seq.clock_gate %[[CLOCK]], %[[VAL_2]]
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// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[VAL_6]] : i32
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// CHECK: %[[VAL_8:.*]] = seq.compreg sym @p0_stage0_reg1 %[[VAL_0]], %[[VAL_6]] : i32
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// CHECK: %[[VAL_9:.*]] = hw.constant false
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// CHECK: %[[VAL_10:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[CLOCK]] reset %[[VAL_4]], %[[VAL_9]] : i1
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// CHECK: %[[VAL_11:.*]] = comb.add %[[VAL_7]], %[[VAL_8]] : i32
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// CHECK: hw.output %[[VAL_11]], %[[VAL_10]] : i32, i1
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// CHECK: }
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hw.module @testSingle(in %arg0: i32, in %arg1: i32, in %go: i1, in %clk: !seq.clock, in %rst: i1, out out0: i32, out out1: i1) {
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%0:2 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32){
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%1 = comb.sub %a0,%a1 : i32
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pipeline.stage ^bb1 regs(%1 : i32, %a0 : i32)
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^bb1(%6: i32, %7: i32, %s1_enable : i1): // pred: ^bb1
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%8 = comb.add %6, %7 : i32
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pipeline.return %8 : i32
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}
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hw.output %0#0, %0#1 : i32, i1
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}
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