mirror of https://github.com/llvm/circt.git
314 lines
15 KiB
MLIR
314 lines
15 KiB
MLIR
// RUN: circt-opt %s -lower-loopschedule-to-calyx -split-input-file | FileCheck %s
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// CHECK: module attributes {calyx.entrypoint = "minimal"} {
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// CHECK: calyx.component @minimal
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// CHECK-DAG: %[[TRUE:.+]] = hw.constant true
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// CHECK-DAG: %[[C0:.+]] = hw.constant 0 : i64
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// CHECK-DAG: %[[C10:.+]] = hw.constant 10 : i64
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// CHECK-DAG: %[[ADD_LEFT:.+]], %[[ADD_RIGHT:.+]], %[[ADD_OUT:.+]] = calyx.std_add
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// CHECK-DAG: %[[LT_LEFT:.+]], %[[LT_RIGHT:.+]], %[[LT_OUT:.+]] = calyx.std_lt
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// CHECK-DAG: %[[ITER_ARG_IN:.+]], %[[ITER_ARG_EN:.+]], %while_0_arg0_reg.clk, %while_0_arg0_reg.reset, %[[ITER_ARG_OUT:.+]], %[[ITER_ARG_DONE:.+]] = calyx.register
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// CHECK: calyx.wires
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// CHECK-DAG: calyx.group @[[INIT_GROUP:.+]] {
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// CHECK-DAG: calyx.assign %[[ITER_ARG_IN]] = %[[C0]] : i64
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// CHECK-DAG: calyx.assign %[[ITER_ARG_EN]] = %[[TRUE]] : i1
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// CHECK-DAG: calyx.group_done %[[ITER_ARG_DONE]] : i1
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// CHECK-DAG: calyx.comb_group @[[COND_GROUP:.+]] {
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// CHECK-DAG: calyx.assign %[[LT_LEFT]] = %[[ITER_ARG_OUT]] : i64
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// CHECK-DAG: calyx.assign %[[LT_RIGHT]] = %[[C10]] : i64
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// CHECK-DAG: calyx.group @[[COMPUTE_GROUP:.+]] {
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// CHECK-DAG: calyx.assign %[[ITER_ARG_IN]] = %[[ADD_OUT]] : i64
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// CHECK-DAG: calyx.assign %[[ITER_ARG_EN]] = %[[TRUE]] : i1
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// CHECK-DAG: calyx.assign %[[ADD_LEFT]] = %[[ITER_ARG_OUT]] : i64
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// CHECK-DAG: calyx.assign %[[ADD_RIGHT]] = %c1_i64 : i64
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// CHECK-DAG: calyx.group_done %[[ITER_ARG_DONE]] : i1
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// CHECK: calyx.control
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// CHECK-NEXT: calyx.seq
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// CHECK-NEXT: calyx.par
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// CHECK-NEXT: calyx.enable @[[INIT_GROUP]]
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// CHECK-NEXT: }
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// CHECK-NEXT: calyx.while %[[LT_OUT]] with @[[COND_GROUP]]
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// CHECK-NEXT: calyx.par
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// CHECK-NEXT: calyx.enable @[[COMPUTE_GROUP]]
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// CHECK-NEXT: }
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// CHECK-NEXT: } {bound = 10 : i64}
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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func.func @minimal() {
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%c0_i64 = arith.constant 0 : i64
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%c10_i64 = arith.constant 10 : i64
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%c1_i64 = arith.constant 1 : i64
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loopschedule.pipeline II = 1 trip_count = 10 iter_args(%arg0 = %c0_i64) : (i64) -> () {
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%0 = arith.cmpi ult, %arg0, %c10_i64 : i64
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loopschedule.register %0 : i1
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} do {
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%0 = loopschedule.pipeline.stage start = 0 {
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%1 = arith.addi %arg0, %c1_i64 : i64
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loopschedule.register %1 : i64
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} : i64
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loopschedule.terminator iter_args(%0), results() : (i64) -> ()
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}
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return
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}
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// -----
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// CHECK: module attributes {calyx.entrypoint = "dot"} {
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// CHECK: calyx.component @dot(%[[MEM0_READ:.+]]: i32 {mem = {id = 0 : i32, tag = "read_data"}}, {{.+}}, %[[MEM1_READ:.+]]: i32 {mem = {id = 1 : i32, tag = "read_data"}}, {{.+}}) -> ({{.+}} %[[MEM0_ADDR:.+]]: i6 {mem = {addr_idx = 0 : i32, id = 0 : i32, tag = "addr"}}, {{.+}} %[[MEM1_ADDR:.+]]: i6 {mem = {addr_idx = 0 : i32, id = 1 : i32, tag = "addr"}}, {{.+}} %[[OUT:.+]]: i32, {{.+}}) {
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// CHECK-DAG: %[[TRUE:.+]] = hw.constant true
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// CHECK-DAG: %[[C0:.+]] = hw.constant 0 : i32
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// CHECK-DAG: %[[C64:.+]] = hw.constant 64 : i32
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// CHECK-DAG: %[[C1:.+]] = hw.constant 1 : i32
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// CHECK-DAG: %[[SLICE0_IN:.+]], %[[SLICE0_OUT:.+]] = calyx.std_slice @std_slice_0
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// CHECK-DAG: %[[SLICE1_IN:.+]], %[[SLICE1_OUT:.+]] = calyx.std_slice @std_slice_1
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// CHECK-DAG: %[[ADD0_LEFT:.+]], %[[ADD0_RIGHT:.+]], %[[ADD0_OUT:.+]] = calyx.std_add @std_add_0
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// CHECK-DAG: %[[ADD1_LEFT:.+]], %[[ADD1_RIGHT:.+]], %[[ADD1_OUT:.+]] = calyx.std_add @std_add_1
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// CHECK-DAG: {{.+}}, {{.+}}, %[[MUL_GO:.+]], %[[MUL_LEFT:.+]], %[[MUL_RIGHT:.+]], %[[MUL_OUT:.+]], %[[MUL_DONE:.+]] = calyx.std_mult_pipe
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// CHECK-DAG: %[[LT_LEFT:.+]], %[[LT_RIGHT:.+]], %[[LT_OUT:.+]] = calyx.std_lt
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// CHECK-DAG: %[[ITER_ARG0_IN:.+]], %[[ITER_ARG0_EN:.+]], {{.+}}, {{.+}}, %[[ITER_ARG0_OUT:.+]], %[[ITER_ARG0_DONE:.+]] = calyx.register @while_0_arg0_reg
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// CHECK-DAG: %[[ITER_ARG1_IN:.+]], %[[ITER_ARG1_EN:.+]], {{.+}}, {{.+}}, %[[ITER_ARG1_OUT:.+]], %[[ITER_ARG1_DONE:.+]] = calyx.register @while_0_arg1_reg
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// CHECK-DAG: %[[S0_REG0_IN:.+]], %[[S0_REG0_EN:.+]], {{.+}}, {{.+}}, %[[S0_REG0_OUT:.+]], %[[S0_REG0_DONE:.+]] = calyx.register @stage_0_register_0_reg
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// CHECK-DAG: %[[S0_REG1_IN:.+]], %[[S0_REG1_EN:.+]], {{.+}}, {{.+}}, %[[S0_REG1_OUT:.+]], %[[S0_REG1_DONE:.+]] = calyx.register @stage_0_register_1_reg
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// CHECK-DAG: %[[S1_REG0_IN:.+]], %[[S1_REG0_EN:.+]], {{.+}}, {{.+}}, %[[S1_REG0_OUT:.+]], %[[S1_REG0_DONE:.+]] = calyx.register @stage_1_register_0_reg
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// CHECK-DAG: %[[RET_IN:.+]], %[[RET_EN:.+]], {{.+}}, {{.+}}, %[[RET_OUT:.+]], %[[RET_DONE:.+]] = calyx.register @ret_arg0_reg
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// CHECK: calyx.wires
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// CHECK-DAG: calyx.assign %[[OUT]] = %[[RET_OUT]]
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// CHECK-DAG: calyx.group @[[INIT_GROUP0:.+]] {
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// CHECK-DAG: calyx.assign %[[ITER_ARG0_IN]] = %[[C0]]
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// CHECK-DAG: calyx.assign %[[ITER_ARG0_EN]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[ITER_ARG0_DONE]]
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// CHECK-DAG: calyx.group @[[INIT_GROUP1:.+]] {
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// CHECK-DAG: calyx.assign %[[ITER_ARG1_IN]] = %[[C0]]
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// CHECK-DAG: calyx.assign %[[ITER_ARG1_EN]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[ITER_ARG1_DONE]]
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// CHECK-DAG: calyx.comb_group @[[COND_GROUP:.+]] {
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// CHECK-DAG: calyx.assign %[[LT_LEFT]] = %[[ITER_ARG0_OUT]]
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// CHECK-DAG: calyx.assign %[[LT_RIGHT]] = %[[C64]]
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// CHECK-DAG: calyx.group @[[S0_GROUP0:.+]] {
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// CHECK-DAG: calyx.assign %[[SLICE1_IN]] = %[[ITER_ARG0_OUT]]
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// CHECK-DAG: calyx.assign %[[MEM0_ADDR]] = %[[SLICE1_OUT]]
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// CHECK-DAG: calyx.assign %[[S0_REG0_IN]] = %[[MEM0_READ]]
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// CHECK-DAG: calyx.assign %[[S0_REG0_EN]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[S0_REG0_DONE]]
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// CHECK-DAG: calyx.group @[[S0_GROUP1:.+]] {
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// CHECK-DAG: calyx.assign %[[SLICE0_IN]] = %[[ITER_ARG0_OUT]]
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// CHECK-DAG: calyx.assign %[[MEM1_ADDR]] = %[[SLICE0_OUT]]
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// CHECK-DAG: calyx.assign %[[S0_REG1_IN]] = %[[MEM1_READ]]
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// CHECK-DAG: calyx.assign %[[S0_REG1_EN]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[S0_REG1_DONE]]
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// CHECK-DAG: calyx.group @[[S0_GROUP2:.+]] {
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// CHECK-DAG: calyx.assign %[[ADD0_LEFT]] = %[[ITER_ARG0_OUT]]
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// CHECK-DAG: calyx.assign %[[ADD0_RIGHT]] = %[[C1]]
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// CHECK-DAG: calyx.assign %[[ITER_ARG0_IN]] = %[[ADD0_OUT]]
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// CHECK-DAG: calyx.assign %[[ITER_ARG0_EN]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[ITER_ARG0_DONE]]
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// CHECK-DAG: calyx.group @[[S1_GROUP0:.+]] {
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// CHECK-DAG: calyx.assign %[[MUL_LEFT]] = %[[S0_REG0_OUT]]
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// CHECK-DAG: calyx.assign %[[MUL_RIGHT]] = %[[S0_REG1_OUT]]
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// CHECK-DAG: calyx.assign %[[S1_REG0_IN]] = %[[MUL_OUT]]
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// CHECK-DAG: calyx.assign %[[S1_REG0_EN]] = %[[MUL_DONE]]
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// CHECK-DAG: calyx.assign %[[MUL_GO]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[S1_REG0_DONE]]
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// CHECK-DAG: calyx.group @[[S2_GROUP0:.+]] {
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// CHECK-DAG: calyx.assign %[[ADD1_LEFT]] = %[[ITER_ARG1_OUT]]
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// CHECK-DAG: calyx.assign %[[ADD1_RIGHT]] = %[[S1_REG0_OUT]]
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// CHECK-DAG: calyx.assign %[[ITER_ARG1_IN]] = %[[ADD1_OUT]]
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// CHECK-DAG: calyx.assign %[[ITER_ARG1_EN]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[ITER_ARG1_DONE]]
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// CHECK-DAG: calyx.group @[[RET_GROUP:.+]] {
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// CHECK-DAG: calyx.assign %[[RET_IN]] = %[[ITER_ARG1_OUT]]
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// CHECK-DAG: calyx.assign %[[RET_EN]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[RET_DONE]]
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// CHECK: calyx.control
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// CHECK-NEXT: calyx.seq {
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// CHECK-NEXT: calyx.seq {
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// CHECK-NEXT: calyx.par {
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// CHECK-NEXT: calyx.enable @[[INIT_GROUP0]]
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// CHECK-NEXT: calyx.enable @[[INIT_GROUP1]]
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// CHECK-NEXT: }
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// CHECK-NEXT: calyx.par {
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// CHECK-NEXT: calyx.enable @[[S0_GROUP0]]
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// CHECK-NEXT: calyx.enable @[[S0_GROUP1]]
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// CHECK-NEXT: calyx.enable @[[S0_GROUP2]]
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// CHECK-NEXT: }
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// CHECK-NEXT: calyx.par {
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// CHECK-NEXT: calyx.enable @[[S0_GROUP0]]
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// CHECK-NEXT: calyx.enable @[[S0_GROUP1]]
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// CHECK-NEXT: calyx.enable @[[S0_GROUP2]]
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// CHECK-NEXT: calyx.enable @[[S1_GROUP0]]
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// CHECK-NEXT: }
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// CHECK-NEXT: calyx.while %[[LT_OUT]] with @[[COND_GROUP]] {
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// CHECK-NEXT: calyx.par {
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// CHECK-NEXT: calyx.enable @[[S0_GROUP0]]
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// CHECK-NEXT: calyx.enable @[[S0_GROUP1]]
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// CHECK-NEXT: calyx.enable @[[S0_GROUP2]]
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// CHECK-NEXT: calyx.enable @[[S1_GROUP0]]
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// CHECK-NEXT: calyx.enable @[[S2_GROUP0]]
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// CHECK-NEXT: }
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// CHECK-NEXT: } {bound = 3 : i64}
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// CHECK-NEXT: calyx.par {
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// CHECK-NEXT: calyx.enable @[[S1_GROUP0]]
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// CHECK-NEXT: calyx.enable @[[S2_GROUP0]]
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// CHECK-NEXT: }
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// CHECK-NEXT: calyx.par {
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// CHECK-NEXT: calyx.enable @[[S2_GROUP0]]
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// CHECK-NEXT: }
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// CHECK-NEXT: calyx.enable @[[RET_GROUP]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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func.func @dot(%arg0: memref<64xi32>, %arg1: memref<64xi32>) -> i32 {
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%c0_i32 = arith.constant 0 : i32
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%c0 = arith.constant 0 : index
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%c64 = arith.constant 64 : index
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%c1 = arith.constant 1 : index
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%0 = loopschedule.pipeline II = 1 trip_count = 5 iter_args(%arg2 = %c0, %arg3 = %c0_i32) : (index, i32) -> i32 {
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%1 = arith.cmpi ult, %arg2, %c64 : index
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loopschedule.register %1 : i1
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} do {
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%1:3 = loopschedule.pipeline.stage start = 0 {
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%4 = memref.load %arg0[%arg2] : memref<64xi32>
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%5 = memref.load %arg1[%arg2] : memref<64xi32>
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%6 = arith.addi %arg2, %c1 : index
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loopschedule.register %4, %5, %6 : i32, i32, index
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} : i32, i32, index
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%2 = loopschedule.pipeline.stage start = 1 {
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%4 = arith.muli %1#0, %1#1 : i32
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loopschedule.register %4 : i32
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} : i32
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%3 = loopschedule.pipeline.stage start = 4 {
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%4 = arith.addi %arg3, %2 : i32
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loopschedule.register %4 : i32
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} : i32
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loopschedule.terminator iter_args(%1#2, %3), results(%3) : (index, i32) -> i32
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}
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return %0 : i32
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}
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// -----
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// Verify that independent store operations are still pipelined.
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// See: https://github.com/llvm/circt/issues/3112
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// CHECK: module attributes {calyx.entrypoint = "store"} {
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// CHECK: calyx.component @store({{.+}}, {{.+}}, {{.+}}, %[[MEM1_DONE:.+]]: i1 {mem = {id = 1 : i32, tag = "done"}}, {{.+}}) -> ({{.+}}, %[[MEM1_WRITE_DATA:.+]]: i32 {mem = {id = 1 : i32, tag = "write_data"}}, %[[MEM1_ADDR0:.+]]: i2 {mem = {addr_idx = 0 : i32, id = 1 : i32, tag = "addr"}}, %[[MEM1_WRITE_EN:.+]]: i1 {mem = {id = 1 : i32, tag = "write_en"}}, {{.+}}) {
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// CHECK-DAG: %[[SLICE0_IN:.+]], %[[SLICE0_OUT:.+]] = calyx.std_slice @std_slice_0
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// CHECK-DAG: {{.+}}, {{.+}}, {{.+}}, {{.+}}, %[[S0_REG0_OUT:.+]], {{.+}} = calyx.register @stage_0_register_0_reg
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// CHECK-DAG: {{.+}}, {{.+}}, {{.+}}, {{.+}}, %[[ITER_ARG0_OUT:.+]], {{.+}} = calyx.register @while_0_arg0_reg
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// CHECK-DAG: {{.+}}, {{.+}}, %[[LT_OUT:.+]] = calyx.std_lt
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// CHECK-DAG: %[[TRUE:.+]] = hw.constant true
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// CHECK: calyx.group @[[INIT_GROUP:.+]] {
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// CHECK: calyx.comb_group @[[COND_GROUP:.+]] {
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// CHECK: calyx.group @[[LOAD_GROUP:.+]] {
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// CHECK: calyx.group @[[INCR_GROUP:.+]] {
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// CHECK: calyx.group @[[STORE_GROUP1:.+]] {
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// CHECK: calyx.group @[[STORE_GROUP2:.+]] {
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// CHECK-DAG: calyx.assign %[[SLICE0_IN]] = %[[ITER_ARG0_OUT]]
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// CHECK-DAG: calyx.assign %[[MEM1_WRITE_DATA]] = %[[S0_REG0_OUT]]
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// CHECK-DAG: calyx.assign %[[MEM1_ADDR]] = %[[SLICE0_OUT]]
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// CHECK-DAG: calyx.assign %[[MEM1_WRITE_EN]] = %[[TRUE]]
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// CHECK-DAG: calyx.group_done %[[MEM1_DONE]]
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// CHECK: calyx.while %[[LT_OUT]] with @[[COND_GROUP]] {
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// CHECK-NEXT: calyx.par {
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// CHECK-NEXT: calyx.enable @[[LOAD_GROUP]]
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// CHECK-NEXT: calyx.enable @[[INCR_GROUP]]
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// CHECK-NEXT: calyx.enable @[[STORE_GROUP1]]
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// CHECK-NEXT: calyx.enable @[[STORE_GROUP2]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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module {
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func.func @store(%arg0: memref<4xi32>, %arg1: memref<4xi32>) {
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%c0 = arith.constant 0 : index
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%c4 = arith.constant 4 : index
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%c1 = arith.constant 1 : index
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loopschedule.pipeline II = 1 trip_count = 4 iter_args(%arg2 = %c0) : (index) -> () {
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%0 = arith.cmpi ult, %arg2, %c4 : index
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loopschedule.register %0 : i1
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} do {
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%0:2 = loopschedule.pipeline.stage start = 0 {
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%1 = memref.load %arg0[%arg2] : memref<4xi32>
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%2 = arith.addi %arg2, %c1 : index
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loopschedule.register %1, %2 : i32, index
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} : i32, index
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loopschedule.pipeline.stage start = 1 {
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memref.store %0#0, %arg1[%arg2] : memref<4xi32>
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memref.store %0#0, %arg1[%arg2] : memref<4xi32>
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loopschedule.register
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}
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loopschedule.terminator iter_args(%0#1), results() : (index) -> ()
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}
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return
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}
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}
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// -----
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// Convert memrefs w/o shape (e.g., memref<i32>) to 1 dimensional Calyx memories
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// of size 1
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// CHECK-DAG: %mem_0.addr0, %mem_0.write_data, %mem_0.write_en, %mem_0.clk, %mem_0.read_data, %mem_0.done = calyx.memory @mem_0 <[1] x 32> [1] {external = true} : i1, i32, i1, i1, i32, i1
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//CHECK-NEXT: calyx.wires {
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//CHECK-NEXT: calyx.group @bb0_0 {
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//CHECK-NEXT: calyx.assign %mem_0.addr0 = %false : i1
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//CHECK-NEXT: calyx.assign %mem_0.write_data = %c1_i32 : i32
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//CHECK-NEXT: calyx.assign %mem_0.write_en = %true : i1
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//CHECK-NEXT: calyx.group_done %mem_0.done : i1
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//CHECK-NEXT: }
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//CHECK-NEXT: }
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module {
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func.func @main() {
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%c1_i32 = arith.constant 1 : i32
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%alloca = memref.alloca() : memref<i32>
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memref.store %c1_i32, %alloca[] : memref<i32>
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return
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}
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}
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// -----
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// Pipeline register to pipeline register writes are valid.
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//CHECK: calyx.group @bb0_3 {
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//CHECK-NEXT: calyx.assign %stage_1_register_0_reg.in = %stage_0_register_0_reg.out : i32
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//CHECK-NEXT: calyx.assign %stage_1_register_0_reg.write_en = %true : i1
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//CHECK-NEXT: calyx.group_done %stage_1_register_0_reg.done : i1
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//CHECK-NEXT: }
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//CHECK-NEXT: calyx.group @bb0_4 {
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//CHECK-NEXT: calyx.assign %stage_2_register_0_reg.in = %stage_1_register_0_reg.out : i32
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//CHECK-NEXT: calyx.assign %stage_2_register_0_reg.write_en = %true : i1
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//CHECK-NEXT: calyx.group_done %stage_2_register_0_reg.done : i1
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//CHECK-NEXT: }
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module {
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func.func @foo(%arg0: i32, %arg1: memref<30x30xi32>) attributes {llvm.linkage = #llvm.linkage<external>} {
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%alloca = memref.alloca() : memref<30x30xi32>
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cf.br ^bb4
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^bb4:
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%0 = arith.constant 0 : index
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%c1_5 = arith.constant 1 : index
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loopschedule.pipeline II = 2 trip_count = 20 iter_args(%arg5 = %0) : (index) -> () {
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%6 = arith.cmpi ult, %arg5, %0 : index
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loopschedule.register %6 : i1
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} do {
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%6:2 = loopschedule.pipeline.stage start = 0 {
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%10 = memref.load %arg1[%0, %0] : memref<30x30xi32>
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%11 = arith.addi %arg5, %c1_5 : index
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loopschedule.register %10, %11 : i32, index
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} : i32, index
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%7 = loopschedule.pipeline.stage start = 1 {
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loopschedule.register %6#0 : i32
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} : i32
|
|
%8 = loopschedule.pipeline.stage start = 2 {
|
|
loopschedule.register %7 : i32
|
|
} : i32
|
|
loopschedule.terminator iter_args(%6#1), results() : (index) -> ()
|
|
}
|
|
cf.br ^bb6
|
|
^bb6:
|
|
return
|
|
}
|
|
}
|
|
|