mirror of https://github.com/llvm/circt.git
139 lines
6.0 KiB
MLIR
139 lines
6.0 KiB
MLIR
// RUN: circt-opt %s -lower-calyx-to-hw | FileCheck %s
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// Sample program:
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//
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// component main(a: 32, b: 32) -> (out: 32) {
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// cells {
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// add = std_add(32);
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// buf = std_reg(32);
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// }
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//
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// wires {
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// out = buf.out;
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// group g0 {
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// add.left = a;
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// add.right = b;
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// buf.in = add.out;
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// buf.write_en = 1'd1;
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// g0[done] = buf.done;
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// }
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// }
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//
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// control {
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// g0;
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// }
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// }
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//
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// Compiled with:
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//
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// futil -p pre-opt -p compile -p post-opt -p lower -p lower-guards -b mlir
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// module attributes {calyx.entrypoint = "main"} {
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calyx.component @main(%a: i32, %b: i32, %go: i1 {go = 1 : i64}, %clk: i1 {clk = 1 : i64}, %reset: i1 {reset = 1 : i64}) -> (%out: i32, %done: i1 {done = 1 : i64}) {
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// CHECK-DAG: %out = sv.wire
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// CHECK-DAG: %[[OUT_VAL:.+]] = sv.read_inout %out
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// CHECK-DAG: %done = sv.wire
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// CHECK-DAG: %[[DONE_VAL:.+]] = sv.read_inout %done
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// CHECK-DAG: %add_left = sv.wire
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// CHECK-DAG: %[[ADD_LEFT_VAL:.+]] = sv.read_inout %add_left
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// CHECK-DAG: %add_right = sv.wire
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// CHECK-DAG: %[[ADD_RIGHT_VAL:.+]] = sv.read_inout %add_right
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// CHECK-DAG: %[[ADD:.+]] = comb.add %[[ADD_LEFT_VAL]], %[[ADD_RIGHT_VAL]]
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// CHECK-DAG: %add_out = sv.wire
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// CHECK-DAG: sv.assign %add_out, %[[ADD]]
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// CHECK-DAG: %[[ADD_OUT_VAL:.+]] = sv.read_inout %add_out
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%add.left, %add.right, %add.out = calyx.std_add @add : i32, i32, i32
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// CHECK-DAG: %buf_in = sv.wire
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// CHECK-DAG: %[[BUF_IN_VAL:.+]] = sv.read_inout %buf_in
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// CHECK-DAG: %buf_write_en = sv.wire
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// CHECK-DAG: %[[BUF_WRITE_EN_VAL:.+]] = sv.read_inout %buf_write_en
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// CHECK-DAG: %buf_clk = sv.wire
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// CHECK-DAG: %[[BUF_CLK_VAL:.+]] = sv.read_inout %buf_clk
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// CHECK-DAG: %buf_reset = sv.wire
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// CHECK-DAG: %[[BUF_RESET_VAL:.+]] = sv.read_inout %buf_reset
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// CHECK-DAG: %[[FALSE:.+]] = hw.constant false
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// CHECK-DAG: %[[SEQ_CLK:.+]] = seq.to_clock %[[BUF_CLK_VAL]]
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// CHECK-DAG: %[[BUF_DONE_REG:.+]] = seq.compreg sym @buf_done_reg %[[BUF_WRITE_EN_VAL]], %[[SEQ_CLK]] reset %[[BUF_RESET_VAL]], %[[FALSE]] : i1
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// CHECK-DAG: %buf_done = sv.wire
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// CHECK-DAG: sv.assign %buf_done, %[[BUF_DONE_REG]]
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// CHECK-DAG: %[[BUF_DONE_VAL:.+]] = sv.read_inout %buf_done
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// CHECK-DAG: %[[TRUE:.+]] = hw.constant true
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// CHECK-DAG: %[[BUF_DONE_VAL_NEG:.+]] = comb.xor %[[BUF_DONE_VAL]], %true : i1
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// CHECK-DAG: %[[BUF_REG_WRITE_EN:.+]] = comb.and %[[BUF_WRITE_EN_VAL]], %[[BUF_DONE_VAL_NEG]] : i1
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// CHECK-DAG: %[[C0_I32:.+]] = hw.constant 0 : i32
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// CHECK-DAG: %[[BUF_REG:.+]] = seq.compreg.ce sym @buf_reg %[[BUF_IN_VAL]], %[[SEQ_CLK]], %[[BUF_REG_WRITE_EN]] reset %[[BUF_RESET_VAL]], %[[C0_I32]]
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// CHECK-DAG: %buf = sv.wire
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// CHECK-DAG: sv.assign %buf, %[[BUF_REG]]
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// CHECK-DAG: %[[BUF_VAL:.+]] = sv.read_inout %buf
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%buf.in, %buf.write_en, %buf.clk, %buf.reset, %buf.out, %buf.done = calyx.register @buf : i32, i1, i1, i1, i32, i1
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// CHECK-DAG: %g0_go = sv.wire
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// CHECK-DAG: %[[G0_GO_VAL:.+]] = sv.read_inout %g0_go
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%g0_go.in, %g0_go.out = calyx.std_wire @g0_go {generated = 1 : i64} : i1, i1
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// CHECK-DAG: %g0_done = sv.wire
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// CHECK-DAG: %[[G0_DONE_VAL:.+]] = sv.read_inout %g0_done
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%g0_done.in, %g0_done.out = calyx.std_wire @g0_done {generated = 1 : i64} : i1, i1
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calyx.wires {
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// CHECK-DAG: %[[TRUE:.+]] = hw.constant true
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%true = hw.constant true
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// CHECK-DAG: %[[FALSE_0:.+]] = hw.constant false
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// CHECK-DAG: %[[VAL_TO_DONE:.+]] = comb.mux %[[G0_DONE_VAL]], %[[TRUE]], %[[FALSE_0]]
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// CHECK-DAG: sv.assign %done, %[[VAL_TO_DONE]]
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calyx.assign %done = %g0_done.out ? %true : i1
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// CHECK-DAG: %[[C0_I32_0:.+]] = hw.constant 0
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// CHECK-DAG: %[[VAL_TO_OUT:.+]] = comb.mux %[[TRUE]], %[[BUF_VAL]], %[[C0_I32_0]]
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// CHECK-DAG: sv.assign %out, %[[VAL_TO_OUT]]
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calyx.assign %out = %true ? %buf.out : i32
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// CHECK-DAG: %[[C0_I32_1:.+]] = hw.constant 0
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// CHECK-DAG: %[[ADD_LEFT_IN:.+]] = comb.mux %[[G0_GO_VAL]], %a, %[[C0_I32_1]]
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// CHECK-DAG: sv.assign %add_left, %[[ADD_LEFT_IN]]
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calyx.assign %add.left = %g0_go.out ? %a : i32
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// CHECK-DAG: %[[C0_I32_2:.+]] = hw.constant 0
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// CHECK-DAG: %[[ADD_RIGHT_IN:.+]] = comb.mux %[[G0_GO_VAL]], %b, %[[C0_I32_2]]
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// CHECK-DAG: sv.assign %add_right, %[[ADD_RIGHT_IN]]
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calyx.assign %add.right = %g0_go.out ? %b : i32
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// CHECK-DAG: %[[FALSE_1:.+]] = hw.constant false
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// CHECK-DAG: %[[BUF_CLK_IN:.+]] = comb.mux %[[TRUE]], %clk, %[[FALSE_1]]
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// CHECK-DAG: sv.assign %buf_clk, %[[BUF_CLK_IN]] : i1
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calyx.assign %buf.clk = %true ? %clk : i1
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// CHECK-DAG: %[[C0_I32_3:.+]] = hw.constant 0
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// CHECK-DAG: %[[BUF_IN_IN:.+]] = comb.mux %[[G0_GO_VAL]], %[[ADD_OUT_VAL]], %[[C0_I32_3]]
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// CHECK-DAG: sv.assign %buf_in, %[[BUF_IN_IN]]
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calyx.assign %buf.in = %g0_go.out ? %add.out : i32
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// CHECK-DAG: %[[FALSE_2:.+]] = hw.constant false
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// CHECK-DAG: %[[BUF_RESET_IN:.+]] = comb.mux %[[TRUE]], %reset, %[[FALSE_2]]
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// CHECK-DAG: sv.assign %buf_reset, %[[BUF_RESET_IN]]
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calyx.assign %buf.reset = %true ? %reset : i1
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// CHECK-DAG: %[[FALSE_3:.+]] = hw.constant false
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// CHECK-DAG: %[[BUF_WRITE_EN_IN:.+]] = comb.mux %[[G0_GO_VAL]], %[[TRUE]], %[[FALSE_3]]
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// CHECK-DAG: sv.assign %buf_write_en, %[[BUF_WRITE_EN_IN]]
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calyx.assign %buf.write_en = %g0_go.out ? %true : i1
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// CHECK-DAG: %[[FALSE_4:.+]] = hw.constant false
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// CHECK-DAG: %[[G0_DONE_IN:.+]] = comb.mux %[[TRUE]], %[[BUF_DONE_VAL]], %[[FALSE_4]]
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// CHECK-DAG: sv.assign %g0_done, %[[G0_DONE_IN]]
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calyx.assign %g0_done.in = %true ? %buf.done : i1
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// CHECK-DAG: %[[FALSE_5:.+]] = hw.constant false
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// CHECK-DAG: %[[G0_GO_IN:.+]] = comb.mux %[[TRUE]], %go, %[[FALSE_5]]
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// CHECK-DAG: sv.assign %g0_go, %[[G0_GO_IN]]
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calyx.assign %g0_go.in = %true ? %go : i1
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// CHECK-DAG: hw.output %[[OUT_VAL]], %[[DONE_VAL]]
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}
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calyx.control {
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}
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}
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// }
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