mirror of https://github.com/llvm/circt.git
120 lines
4.6 KiB
MLIR
120 lines
4.6 KiB
MLIR
// RUN: circt-opt -pass-pipeline='builtin.module(calyx.component(materialize-calyx-to-fsm))' %s | FileCheck %s
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// CHECK: fsm.machine @control(%[[A_DONE:.*]]: i1, %[[B_DONE:.*]]: i1, %[[COND_DONE:.*]]: i1, %[[TOP_LEVEL_GO:.*]]: i1) -> (i1, i1, i1, i1)
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// CHECK-NEXT: %[[C1:.*]] = hw.constant true
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// CHECK-NEXT: %[[C0:.*]] = hw.constant false
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// CHECK-NEXT: fsm.state @fsm_entry output {
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// CHECK-NEXT: fsm.output %[[C0]], %[[C0]], %[[C0]], %[[C0]] : i1, i1, i1, i1
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @[[SEQ_0_COND:.*]] guard {
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// CHECK-NEXT: fsm.return %[[TOP_LEVEL_GO]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @[[FSM_EXIT:.*]] output {
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// CHECK-NEXT: fsm.output %[[C0]], %[[C0]], %[[C0]], %[[C1]] : i1, i1, i1, i1
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @[[SEQ_1_IF:.*]] output {
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// CHECK-NEXT: fsm.output %[[C0]], %[[C0]], %[[C0]], %[[C0]] : i1, i1, i1, i1
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @[[SEQ_1_IF_THEN_A:.*]] guard {
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// CHECK-NEXT: fsm.return %lt_reg.out
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.transition @[[SEQ_1_IF_ELSE_B:.*]] guard {
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// CHECK-NEXT: %true_2 = hw.constant true
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// CHECK-NEXT: %0 = comb.xor %lt_reg.out, %true_2 : i1
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// CHECK-NEXT: fsm.return %0
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @[[SEQ_1_IF_THEN_A]] output {
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// CHECK-NEXT: fsm.output %[[C1]], %[[C0]], %[[C0]], %[[C0]] : i1, i1, i1, i1
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @[[FSM_EXIT]] guard {
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// CHECK-NEXT: fsm.return %[[A_DONE]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @[[SEQ_1_IF_ELSE_B]] output {
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// CHECK-NEXT: fsm.output %[[C0]], %[[C1]], %[[C0]], %[[C0]] : i1, i1, i1, i1
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @[[FSM_EXIT]] guard {
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// CHECK-NEXT: fsm.return %[[B_DONE]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @[[SEQ_0_COND]] output {
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// CHECK-NEXT: fsm.output %[[C0]], %[[C0]], %[[C1]], %[[C0]] : i1, i1, i1, i1
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @[[SEQ_1_IF]] guard {
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// CHECK-NEXT: fsm.return %[[COND_DONE]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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calyx.component @main(%go: i1 {go}, %reset: i1 {reset}, %clk: i1 {clk}) -> (%done: i1 {done}) {
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%false = hw.constant false
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%true = hw.constant true
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%lt_reg.in, %lt_reg.write_en, %lt_reg.clk, %lt_reg.reset, %lt_reg.out, %lt_reg.done = calyx.register @lt_reg : i1, i1, i1, i1, i1, i1
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%t.in, %t.write_en, %t.clk, %t.reset, %t.out, %t.done = calyx.register @t : i1, i1, i1, i1, i1, i1
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%f.in, %f.write_en, %f.clk, %f.reset, %f.out, %f.done = calyx.register @f : i1, i1, i1, i1, i1, i1
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%lt.left, %lt.right, %lt.out = calyx.std_lt @lt : i1, i1, i1
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calyx.wires {
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%0 = calyx.undef : i1
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calyx.group @A {
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%A.go = calyx.group_go %0 : i1
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calyx.assign %t.in = %A.go ? %true : i1
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calyx.assign %t.write_en = %A.go ? %true : i1
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calyx.group_done %t.done : i1
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}
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calyx.group @B {
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%B.go = calyx.group_go %0 : i1
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calyx.assign %f.in = %B.go ? %true : i1
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calyx.assign %f.write_en = %B.go ? %true : i1
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calyx.group_done %f.done : i1
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}
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calyx.group @cond {
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%cond.go = calyx.group_go %0 : i1
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calyx.assign %lt_reg.in = %cond.go ? %lt.out : i1
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calyx.assign %lt_reg.write_en = %cond.go ? %true : i1
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calyx.assign %lt.left = %cond.go ? %true : i1
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calyx.assign %lt.right = %cond.go ? %false : i1
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calyx.group_done %lt_reg.done ? %true : i1
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}
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}
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calyx.control {
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fsm.machine @control() attributes {compiledGroups = [@A, @B, @cond], initialState = "fsm_entry"} {
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fsm.state @fsm_entry transitions {
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fsm.transition @seq_0_cond
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}
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fsm.state @fsm_exit
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fsm.state @seq_1_if transitions {
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fsm.transition @seq_1_if_then_seq_0_A guard {
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fsm.return %lt_reg.out
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}
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fsm.transition @seq_1_if_else_seq_0_B guard {
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%true_0 = hw.constant true
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%0 = comb.xor %lt_reg.out, %true_0 : i1
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fsm.return %0
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}
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}
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fsm.state @seq_1_if_then_seq_0_A output {
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calyx.enable @A
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fsm.output
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} transitions {
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fsm.transition @fsm_exit
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}
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fsm.state @seq_1_if_else_seq_0_B output {
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calyx.enable @B
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fsm.output
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} transitions {
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fsm.transition @fsm_exit
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}
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fsm.state @seq_0_cond output {
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calyx.enable @cond
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fsm.output
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} transitions {
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fsm.transition @seq_1_if
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}
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}
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}
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}
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