Instead of always making registers and memories observable for the user,
add dedicated `--observe-registers` and `--observe-memories` options to
`arcilator`. These allow the user to indicate whether they are
interested in observing or register and memory state. If these options
are set to false, don't attach "name" or "names" attributes to states
and memories, such that other parts of the pipeline have a chance to
delete unnecessary state.
This pass converts wires with flips in their types to wires with passive types. This expands connects to resolve flips effects on data flow. After expansion, flips carry no more information and can be removed from wires (as wires have duplex flow).
Add an option to HGLDD file emission to only consider location
information in the IR if the corresponding file exists on disk. This can
help filter out placeholder filenames such as `<stdin>` or `<unknown>`.
Also add a corresponding `--hgldd-only-existing-file-locs` option to
firtool.
In preparation for FIRRTL 4.0.0, remove CircuitOp's "getMainModule" member
function. This no longer makes sense in FIRRTL 4.0.0 where a circuit may have
any number of public modules and not just one "main" (or top) module.
Reviewed in: https://github.com/llvm/circt/pull/6449
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Remove the -scalarize-top-module option to firtool (and the parser).
Replace this with -scalarize-public-modules. This is done in preparation
for FIRRTL 4.0.0. This is also largely unnecessary once FIRRTL 4.0.0
figures out how to attach the ABI to each public module.
Co-authored-by: Will Dietz <will.dietz@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
There was a bug in FlattenIO, it was crashing for instances of hwModuleExternOp.
If an instance op is flattened before the corresponding module op, then it results in an inconsistent IR.
Fix this issue, by using an explicit InstanceOp builder that doesn't rely on the module op.
Add a flag to control the external module flattening and also enable recursive by default.
Move firtool pipeline configuration over to the same mechanism the rest of llvm and mlir use. Export this via the CAPI. Add a couple examples of methods to change options to the CAPI. Interested parties are encouraged to finish out the set of functions.
Since the CAPI has no tests, this breaks nothing.
As an aside, the configuration space of the firrtl pipeline is WAY too big.
Rename the "GroupSink" pass to "LayerSink" to reflect new language in the
FIRRTL 4.0.0 specification.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Rename the "GroupMerge" pass to "LayerMerge" to reflect the new language
in the FIRRTL 4.0.0 specification.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Change the pass name to reflect the new FIRRTL 4.0.0 specification
language of "layers" instead of "groups".
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Change the FIRRTL Dialect operation GroupOp to be called LayerBlockOp.
This is done to align FIRRTL Dialect with version 4.0.0 of the FIRRTL
Specification. This makes no changes to parsing or emitting FIRRTL.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Rename GroupDeclOp to LayerOp and GroupConvention to LayerConvention.
This is the first piece of applying the FIRRTL 4.0.0 Specification name
change of "group" to "layer".
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
The instance graph is transitioning towards supporting multiple possible targets for instance operations.
As a consequence, it can no longer assume that there are instance operations with a single target and it will expose a generic interface returning a list of targets.
This PR removes the lookup helper from the graph and instead provides the users (`firrtl::InstanceOp` in particular) with helpers to fetch the unique referenced instance.
Rather than identifying cosim endpoints by "%m", have them specified entirely upstream. The easiest way to ensure uniqueness then is to only allow cosim endpoints at the top level. This solves a number of issues, and also makes cosim look a lot more like other ESI services.
Pull the `getPortVerilogName` helper out of `ExportVerilog` and move it
into the `hw::PortInfo` struct as `getVerilogName`. This allows other
passes that run after Verilog emission to query a port's Verilog name
without duplicating that piece of code.
Add a pass that merges optional groups which reference the same
declaration. This exposes additional optimization opportunities and
produces better Verilog output for groups.
Fixes#6228.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Adds a shift register operation to the seq dialect. The operation has an interface similar to a `seq.compreg.ce` operation, with an additional `size` to specify the number of stages.
Included is a default lowering to `seq.compreg.ce` operations. The main intention of introducing this operation is to be able to emit shift registers using target-specific resources.
I don't see a reason to add a non-clock-enabled shift reg operation in addition to this. If users need a non-clock-enabled shift register, it should suffice to emit a shift register with constant 1 clock-enable, whereafter (if lowered to e.g. `seq.compreg.ce`), the lowered primitive should have a canonicalization that considers the constant clock enable signal.
The pass relies on `seq` items, creating a circular dependency between SV and Seq.
It better belongs to the seq dialect, alongside options and ops it related to.
Moving forward, this should be merged into FIR memory lowerings.
The Map property type was not necessary in the end. A Map can easily
be represented by a list of object with two fields, and this is how
its been done downstream. Remove this to simplify FIRRTL and reduce
maintainence burden.
This type wasn't needed after all. We may eventually want some form of
this, but there is no immediate need. Removing this for now reduces
maintainence burden until we are sure what we want.
The ops are consumers of clock signals, so the trait is added.
Additionally, the `clock` operand is renamed into `clk` to keep it consistent with other `seq` ops.
Trace recording and playback could be very useful. Could also be used for design introspection and runtime testing (without cosim). This is the start of that system.
Have the instance op builder try to resolve any parametric types in the module. If it fails, fallback to the parameterized module types and don't print an error message.
This PR changes the HW StructExtract, StructInject, UnionCreate and UnionExtract ops to reference their accessed field by the respective aggregate type's field index instead of the field name. This allows us to access the field's FieldInfo struct directly instead of having to traverse the array to find the matching name.
- Symbol-defining operations nested within `ibis.class` and `ibis.container` ops are now declared as `InnerSymbol`s.
- `ibis.class` is now an `NestedSymbolTable`s.
- `ibis.method` can no longer inherit from `FunctionLike` since that interface is built around an assumption of the function inheriting from `Symbol`.
- Containers are NOT `InnerSymbolTable`s yet - we cannot yet support nested symbol tables; see #6330; given that `ibis.container` needs to be able to still be able to be placed inside an `ibis.class` op.
Given the latter point, this is not a perfect implementation. As such, some parts of the implementation is still underperformant (e.g. `ScopeOpInterface::lookupInnerSym` which essentially does a scan of `InnerSymbol` ops inside the scope to facilitate symbol-lookup-like capability).
However, the implementation solves the immediate goals of:
1. not misusing MLIR by having nested symbol tables and looking across them
2. allowing the use of `hw.instance` operations inside containers nested in classes.
In order to use the types in Python with isinstance, etc., we need to
provide the mlir_type_subclass bindings. This adds the C API
boilerplate and binds the types.
The inclusion of "circt/Dialect/MSFT/MSFTDialect.h" included
"llvm/Support/type_traits.h" which is a C++ header and causes issues
when included from a C compiler.
---------
Co-authored-by: John Demme <john.demme@microsoft.com>
This turned out to be a bad idea. We're still using Cap'nProto for Cosim, just with the message being a blob which is already encoded by the client. This is nearly identical to what happens in hardware, just Cap'nProto/DPI as the transport layer.
Goodbye old frenemy.
Add the `DebugAnalysis` which marks values and operations that only feed
into debug info. This will later allow ExportVerilog to skip expressions
and statements that are exclusively used by debug ops and are irrelevant
for synthesis and simulation.
The analysis is fairly straightforward at the moment. In the future, we
may want to be more clever about what we mark as debug-only. For
example, certain debug info output formats may allow us to emit entire
expressions and state machines, such that those can be stripped from the
Verilog output. In that case, we'd want to look through expressions,
wires, and registers when marking ops as debug-only. But some other
formats may only allow us to point at named signals in the Verilog, such
that any expression or register has to remain in Verilog, and possibly
be visible under a name for the debug info to make use of it.
This commit also bundles the `DebugInfo` analysis, which extracts the
source language hierarchy and variable layout from the IR, together with
this new `DebugAnalysis`, which marks ops as debug-only.
Add an argument to the callback of walkGroundTypes to indicate if the ground type is flipped.
This is required for dataflow analysis of connections of flipped aggregate fields, which is used in #5647
This PR adds a new pass called `Lint` to the `FIRRTL` pipeline, that checks for
operations that are guaranteed to fail a simulation.
Currently the pass detects static asserts, that is an assert which is enabled
and the predicate is either a constant false or a reset. The pass emits an
error on the assert that is guaranteed to fail in simulation.
The pass can later be extended to include more such checks.
When running the service connection pass, leave a record of the original designer intent. Will be used later on for the manifest. Rename AppID.td to Manifest.td.
Add the `MaterializeDebugInfo` pass, which creates debug ops to track
FIRRTL-level ports, nodes, wires, registers, and instances throughout
the pipeline. This is a fairly simple first attempt at tracking
higher-level source language information through the compilation using
the debug dialect.
Also add the `-g` option to firtool, which causes this pass to run very
early on in the pipeline where all the high-level information is still
available. Enabling this option will currently cause `ExportVerilog` to
fail because of the additional operations in the IR -- to be rectified
by a later PR.
This PR factors out some of LowerAnnotation helpers to a header and introduces registerAnnotationRecord method so that downstream user can extend the table.
Fixes#4933.
This change adds evaluator support for frozen paths.
Two new EvaluatorValues have been added, one for BasePaths, which
represent fragments of paths through the instance hiearchy, and one for
Paths, which represent a full path to a hardware component.
When the evaluator instantiates an OM class, it is expected that it will
usually have to pass in an empty basepath, which signifies that the
class is at the top of the hierarchy. To facilitate this, we exposed the
ability to create an empty basepath value in the python API.
Path values can be transformed in to strings, where in they are printed
as FIRRTL style target paths. In the future, we may want a richer API.
Deleted paths are represented as Path values with the targetKind
attribute nulled out, which is handled specially in the string
serializer.
Add the `dbg` dialect, alongside a rationale document, basic types, and
the three essential `dbg.variable`, `dbg.struct`, and `dbg.array`
operations.
The goal is for this dialect to be a home for all the machinery needed
to track debug information in the IR. After discussions with a few
people in the LLVM/MLIR space, I chose to create dedicated operations to
track debug info in the IR, as opposed to an attribute/metadata based
approach. The details are outlined in the rationale document.
Subsequent PRs add simple debug info tracking to FIRRTL and firtool, and
extend debug info emission to consider these operations.
An ESI system manifest is intended to describe the parts of a particular
accelerator which may be relevant to software. It will eventually
replace the services metadata json.
This first PR only outputs types on cosim ports.
Adds a new operation to the MSFT dialect which specifies a multicycle path constraint in between two symbols.
This implementation does not opt in to the whole dynamic instance hierarchy specification of MSFT; do we want to do that? Would have to require some thinking about what it means that a PD constraint refrences two dynamic instances, wherein `msft.instance.dynamic` currently expects all nested pd constraints to reference the parent instance exclusively.
To this, i don't think it will be needed in our immediate usecase, anyways (assuming we're going to use `hw.path.to_this` which itself will generate the `hw.hierpath` and _not_ use the dynamic instance hierarchy support in MSFT).
Also splits `DynInstDataOpInterface` into a two interfaces; one base interface (anything that pertains to dynamic instance data) and the `UnaryDynInstDataOpInterface` which refers to all data ops which access a single location - some additional boilerplate is introduced since the current implementation of OpInterface's doesn't seem to support inheriting interfaces implementing parent interfaces (everything is expected to be defined by the implementing op).
Exported TCL example:
```tcl
proc reg_0_multicycle_config { parent } {
set_multicycle_path -hold 1 -setup 2 -from [get_registers {$parent|reg_0}] -to [get_registers {$parent|reg2}]
}
```
RecursiveMemoryEffects and RecursivelySpeculatable traits provides automatic derivation of side-effects of operations but these effects are computed by recursive IR walk. This is problematic for firrtl.when since when operations are often deeply nested, which prevents us from running canonicalizers before ExpandWhens. This PR just removes these traits and add canonicalizers for whens manually.
This commit adds strip option to drop name pass. Even though there is none option but none option does keep existing names. strip explicitly strips all names to remove variable names form Chisel.
Previously Namespace::newName could return empty string for empty string.
This is a problematic behaivor since primary use cases of Namespace is
symbol generation but empty string cannot be used a symbol.
For example HWExportModuleHierarchy crashed with an instance with an
empty name.
This commit fixes the issue by pre-registering empty string in a constructor of
Namespace.
This PR does an overhaul of how path related operations work in the OM dialect.
When OM classes are created from FIRRTL, a base path is now fed through the
class hieararchy. All paths to hardware objects are now created relative to
the base path. The `path` op has been renamed to `path_create`, and now takes
a basepath SSA parameter, which means that it is impossible to create a path
which is not relative to some base.
A second set of operations to create "frozen paths" have been added. In
FreezePaths, we lower all path operations to hard-coded strings, which allows
us to remove the hardware from the OM IR and still be valid. These operations
have been changed to return `FrozenPathType`, which is to make sure that people
don't try to inter-mix the two kinds of path types. The intention is that the
evaluator will only understand frozen paths.
The PathAttr in OM no longer represents the entire target path, but just the
list of instances which lead up to it.
This also adds an OM utility for parsing FIRRTL style target strings, which is
used in the `frozenpath_create` MLIR assembly format. The existing APIs
contained in FIRRTL were not suitable since these new strings do not include
the circuit name, and we need some restrictions for parsing base paths, which
can not target components. The new parser is a bit more resilient to badly
formed path strings. In the future it may be possible to reunite these two
bodies of code.
The existing python support for paths had to be removed.
Fabian Schuiki