.get() on a type should construct a new type. BaseAlias was using this function to ALSO return the wrapped type. Rename the accessor to not conflict with the factory.
When inlining and flattening FIRRTL instances, create `dbg.scope`
operations to track information about the original hierarchy in the
debug info.
To do this, the FIRRTL inliner now creates a `dbg.scope` op for every
inlined instance. When renaming the operations in the inlined module's
body, debug operations are assigned this scope (unless they already had
a scope assigned). This retains information about the original
hierarchy.
Unfortunately, this approach currently only works for debug variables
and scopes. Instances have no `scope` operand where a parent scope can
be annotated. As a result, instance ops whose parent module got inlined
do not properly track their original scope. This limitation will go away
in the future once we are either able to interact with and modify the
implicit scope created by instances, or instances scopes get passed in
as explicit operands.
Add support for representing an optional layer in each probe type. This
only handles storage and MLIR printing/parsing.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add two helpers for printing boilerplate that is commonly used when
generating LLVM debugging information for passes. This will be used to
replace this boilerplate in passes in a future commit.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Added missing tool in integration test
* Fixed formatting
* Fixed whitespace issue
* Fixed typo in VerilogGeneration.md
* Added skeleton for btor2 lowering pass
* added pattern match skeleton to lowering pass
* Added initial emission of inputs and hw::constant ops
* added constant emission
* added emission for most operations and final assertion
* Added support for muxes, assumptions and wire aliases
* Added support for inputs in btor2
* fixed bug in input generation
* added support for missing comb operations
* Changed input registration to allow for booleans
* Made input type check more robust
* WIP register state transition system generation
* Added support for registers
* refactored hardcoded string
* added names to btor2 states
* Added state initialization support
* Removed state initializer, it should be a firrtl construct and not a btor one
* Removed temporary file emission
* Added back accidentally removed btor2 string printing
* Ran clang-format
* Ran clang-format
* WIP refactored typeswitch
* refactored giant type switch
* Made all string litterals constexpr
* attempting to fix sanity check
* fixed variable name typo
* Attempting to satisfy clang-tidy
* renamed things to make clang happy
* inlined useless helper methods
* Clarified the necessity of important data structures in comments
* fixed formatting
* Changed pass into a Conversion pass
* refactored helper methods
* Checked for case where next is a port when emitted transitions
* Added newline at EOF
* Inherited visitors instead of using a big typeswitch
* Throw an error for unsupported ops and explicitly ignore the rest
* Removed unnecessary functions and refactored runOnOperation
* Fixed formatting
* Attempted to add some test
* Added in ops that weren't covered by visitors
* Added in missing declaration in header
* Included pass in CAPI CmakeLists
* Added infrastructure for btor integration tests
* Revert "Added infrastructure for btor integration tests"
This reverts commit a5ec3da4ec.
* various nitpicking comments accounted for
* used generalized ids for btor2 testcase
* fixed typo in test
* updated test and found small bug
* clang-format
* added support for arbitrary resets
* Updated test to reflect new handling of reset
* Switched to a DFS strategy for emission
* Updated test to align with preemission of register declarations
* Removed gratuitous lookups.
* inlined a bunch of string constatns
* removed certain silent fails and added out of order test
The `SpecializeOptions` pass eliminates instance choices and replaces them with instances targeting the modules associated with a case provided through the options.
This PR defines a ChainingCyclicProblem, which models a hybrid problem of ChainingProblem and CyclicProblem and adapts the simplex scheduler to solve this problem. It is mainly done by reusing and adapting codes from the two base problems. This problem represents the problem a static HLS tool will solve for loop pipelining.
---------
Co-authored-by: leothaud <dylan.leothaud@irisa.fr>
Allow `!arc.state` to carry HW structs and arrays. The state only has to
be able to compute the bit width of the inner type, but it does not care
what exactly this type is.
Rework the Arc-to-LLVM lowering to do the entire lowering in one full
conversion, instead of two separate ones. There is no real need for the
split, and combining all patterns into one large conversion allows all
Arc types to be directly converted to LLVM types. Previously, after the
first partial conversion the IR would be in a strange in-between state
of mixing Arc types into LLVM operations (for example, loads and stores
of HW struct/array types).
Enable the `InferStateProperties` pass in the arcilator pipeline and
make its enable and reset signal detection individually controllable.
The enable portion is already supported by the rest of the arcilator
pipeline and can produce 20%-35% speedup on the cores in arc-tests.
Turn on enable detection by default.
The reset portion is not fully supported yet and causes the simulation
to misbehave. It is disabled by default.
As a minor refactoring this removes the `constructor` field from the
pass definition, such that the constructor and plumbing for options gets
generated automatically. As a side effect, the constructor is now called
`arc::createInferStateProperties` instead of the previous
`arc::createInferStatePropertiesPass`. (Thanks @uenoku for the pointer.)
Shoutout to @maerhart and @TaoBi22 for this fantastic pass!
Add the `dbg.scope` operation to the debug dialect. The op creates an
additional level of hierarchy in the DI, a "scope", which can be used to
group variables and other scopes.
Operations such as `hw.module` introduce an implicit scope. All debug
operations within a module are added to that implicit scope, unless they
have an explicit `scope` operand. Providing an explicit scope can be
used to represent inlined modules.
Scopes in DI do not necessarily have to correspond to levels of a module
hierarchy. They can also be used to model things like control flow
scopes, call stacks, and other source-language concepts.
This commit also introduces an optional `scope` operand on
`dbg.variable`. The `DebugInfo` analysis, which traverses the IR and
builds up a canonical representation of the DI, honors this operand and
adds the variables to the corresponding scope.
The arc dialect currently provides its own `arc.clock_gate` operation.
Since the seq dialect has a proper `seq.clock_gate` now, switch over to
that and remove custom arc op.
Fixes#6500.
Add the `--fixup-eicg-wrapper` option to firtool and the LowerIntrinsics
pass. Setting the option will treat `EICG_wrapper` modules like an
intrinsic and replace them with the `firrtl.int.clock_gate` operation.
In the long run, Chisel/FIRRTL designs will directly emit the clock gate
intrinsic, and `EICG_wrapper` extmodules will be gone. However until we
get there, this option provides an incremental path towards deprecating
the `EICG_wrapper` pattern. It allows us to switch the CIRCT side of the
flow over to the intrinsic without having to make changes to Chisel in
lockstep. Once all relevant existing designs work with this switch
enabled, Chisel projects can opt into emitting clock gates directly, and
can gradually upgrade. At that point we can make firtool emit
deprecation warnings for uses of `EICG_wrapper` extmodules, and at some
point we can entirely drop special handling of these modules altogether.
This switch is disabled by default and does not affect existing flows.
ArrayRef<BlockArgument> makes the elements 'const' unnecessarily,
causing issues with upcoming LLVM bump, due to http://llvm.org/PR72765 .
There's no BlockArgumentRange, so use Block's typedef (=MutableArrayRef).
Andrew Lenharth