Commit Graph

8551 Commits

Author SHA1 Message Date
Martin Erhart 2345382e67
[LLHD] Remove llhd-sim (#7351) 2024-07-19 17:54:14 +01:00
Prithayan Barua dde9f4bc96
[Seq] Canonicalize firreg with a preset (#7350)
The canonicalization was ignoring any registers with a preset, this commit fixes that.
Add fold and canonicalization patterns for registers with a preset.
2024-07-19 09:23:33 -07:00
John Demme 2628ea8533
[ESI Runtime] If zlib not found, use FetchContent (#7352)
Avoids having to use vcpkg on Windows for non-cosim builds.
2024-07-19 05:56:35 -07:00
Schuyler Eldridge 7e78b930ea
[FIRRTL] Test whitespace cleanup, NFC
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2024-07-18 23:11:58 -04:00
Schuyler Eldridge 7807d78ad2
[FIRRTL] Fix Test for Windows, NFC
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2024-07-18 23:11:58 -04:00
Robert Young 7c8a2e195a
[FIRRTL] AssignOutputDirs: Ensure absolute dirs end with trailing slash (#7348)
When making a directory absolute, the remove_dots helper canonicalizes away any
trailing slash. Add the slash back on, which ensures that we interpret the path
as a directory correctly.

This fixes a bug where a path, when LCA'd with itself, drops the last segment.

An example of the problem: given a path foo/bar/, if we drop the trailing
slash, foo/bar is interpreted as a file called bar in a directory called foo.
When we LCA foo/bar with itself, the common parent directory is determined to
be foo/. By retaining the trailing slash, we can ensure that the correct LCA
path foo/bar/ is computed.

Fixes: #7347
2024-07-18 21:26:49 -04:00
Martin Erhart 52e7c2e355
[MooreToCore] Support NegOp lowering (#7344) 2024-07-19 00:42:12 +01:00
Fabian Schuiki b940a5d6c6
[Moore] Make net/variable names optional
Make the `name` attribute of `VariableOp`, `NetOp`, and `AssignedVarOp`
optional in the Moore dialect. The HW dialect does the same thing for
its wire op. Making the name optional allows us to have temporary and
compiler-generated variables without requiring dummy names to be
conjured up.
2024-07-18 15:36:23 -07:00
Fabian Schuiki 7d57cfbc87
[Moore] Make ReadOp infer its result type
Infer the result type of `moore.read` by unpacking the `RefType` of its
operand. This triggers a lot of mechanical changes to the tests. Remove
the type from most `CHECK` lines to make future changes easier.
2024-07-18 15:15:16 -07:00
Fabian Schuiki 846139b8ba
[ImportVerilog] Allow enum variants in expressions (#7339)
Add support for enum variants in expressions. Until now, ImportVerilog
would emit a "unknown name" diagnostic when an enum variant is used in
an expression. This is due to the lowering of named value expressions
simply checking whether an MLIR value is present in the `valueSymbols`
table for the referenced symbol name. This works for variables which
create dedicated declarations, but not for enum variants which
potentially live outside the current module's scope.

Instead, ImportVerilog will now check if the named value is a constant,
for example a parameter or an enum variant, and materialize that
constant directly as a `moore.constant` op. This will also be able to
deal with parameters declared inside of packages, for which the table of
value symbols of the current module does not contain any value. (Local
parameters inside the module generate a `moore.named_constant` op that
is present in the table.)
2024-07-18 10:56:57 -07:00
Michael Maloney f15c4a7a4b
[FIRRTL][FIRParser] Tokenize Commas (#7206)
Due to historical circumstances, the SFC parser for FIRRTL treated commas (`,`) as whitespace. This behavior was carried over into the CIRCT implementation of `firtool`.

This behavior is utterly bizarre. 

Moreover, the FIRRTL spec has indicated comma tokens (`,`) for at least every version since last year. 

This PR removes this quirk and properly tokenizes commas, requiring them in the places dictated by the FIRRTL spec.

The impact of this PR should be low, but it may break code (in CIRCT, in Chisel, and elsewhere) in places where FIRRTL was being emitted with a loose interpretation, or where the spec was ambiguous.

Changes:
* Update several tests which were leaning into the "commas-are-whitespace" behavior.
* Removed `','` from the list of "horizontal whitespace" and added an explicit `FIRToken::comma` token.
* Made changes to the various `parse*()` methods to consume the tokens.
* Note the use of a pattern I found useful in several places where I use a boolean `first` to skip parsing comma tokens on the first iteration. Please check me here, since I learned C++ before lambdas were a thing.
* Made a few judgment calls around unspeced constructs (`smem`).
* * I changed the FIRRTL emitter in one place where the syntax was unspeced, and there seemed to be conflicting examples.
* @seldridge For some reason, it seemed ambiguous whether `layer` decls need commas. I opted *for* commas. I can swap if I got this backwards.
* I added `parseRUW()` as a non-optional variant of `parseOptionalRUW()`, since the comma token can be used to determine optionality in one case.
2024-07-19 02:43:37 +09:00
Fabian Schuiki a3b94620f0
[ImportVerilog] Handle $signed/$unsigned system tasks (#7337)
Handle calls to the `$signed` and `$unsigned` system tasks by simply
passing through the argument. The casting is handled by Slang during
type checking and is materialized as a type conversion node in the AST.
The call itself has no function after that.

The `visitCall` function is going to be the place to add handling for
other system calls in the future. IEEE 1800-2017 section 20 defines a
fairly substantial list of builtin system tasks. Most of these will want
to have a dedicated `moore.builtin.*` op in the future.
2024-07-18 09:55:48 -07:00
Hideto Ueno f9b58a0ddf
[SV] Add UnpackedArrayCreateOp (#7303)
This commit adds unpacked array create op that will be lowered into array literal
 `'{..}`.

Since array literal must be used in assignment-like context,`unpacked_array_create`
is always spilled to a temporary wire.

The operand ordering follows HW array representation. This is currently tricky since
we emit unpacked types slightly differently (`downTo`) but the correct ordering is emitted
in ExportVerilog.
2024-07-18 19:53:12 +09:00
John Demme 880af00242
[ESI Runtime] Backend plugin loading on Windows (#7338)
Turns out Windows python support was missing zlibd1.dll. Also adding backend plugin loading support.
2024-07-18 01:56:46 -07:00
mingzheTerapines b7afc536db
[ImportVerilog] [SROA] [Mem2Reg][Canonicalizers]Support Passes for Nested Type (#7158)
For the new concept of Moore dialect, some operations will be defined as memory-related operations. Modeling memref Dialect and LLVM dialect, the operation relationship is as follows:

ReadOp and blockingAssignOp are related to loadOp and storeOp.
VariableOp is related to allocaOp.
However, the operations mentioned below are for basic types. This PR will support nested types in the following way:

VariableOp with nested types is still related to allocaOp (will be replaced with structCreateOp and UnionCreateOp).
structExtractRefOp is related to storeOp.
structExtractOp is related to loadOp.
To implement this:

Since these operations will be lowered to the hw dialect, the design largely refers to the hw dialect.

Add the trait DestructurableAllocationOpInterface for VariableOp.

Add the trait DestructurableAccessorOpInterface for structExtractOp and structExtractRefOp.

Implement the DestructurableTypeInterface for structLikeType and the reftype of structLikeType.

For local variables:

Use the SROA (Scalar Replacement of Aggregates) Pass to destructure all nested-type variables into basic-type variables.
Use the Mem2Reg (Memory to Register) Pass to replace variables imported by SROA with constants.
For global/module-level variables:

When importing Verilog, use structInjectOp rather than blockingAssignOp, because structExtractRefOp has the Destructurable trait, but global variables should not be destructured.
structInjectOp means creating a new struct with new values and other old values.
Use the canonicalizer Pass to fold duplicate injecting same field operations.
Use the canonicalizer Pass to explicitly show new struct creation.
Use the canonicalizer Pass to send source values directly and remove structExtractOp.
Also, remove some unnecessary spaces in other code.

What's more:

Verify that the input of nested-type-related operations should match the field type defined.
To do:

Update the use of struct SSA values referring to the latest structInjectOp SSA values.
Design the method for union types.
Add and support the dbg dialect to keep local variables visible after SROA & Mem2Reg.

Co-authored-by: Théo Degioanni <degiotheo@gmail.com>
Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
2024-07-18 10:56:37 +08:00
Fabian Schuiki bfb59ad7e8
[ImportVerilog] Accept empty packages (#7334)
Add handling for package definitions and accept empty packages for the
time being. Later on we'll want to support parameters, variables,
functions, and other things that can appear in packages. These require
a mechanism to refer to things outside of an `SVModuleOp` though, which
does not yet exist.
2024-07-17 19:21:13 -07:00
mingzheTerapines d3ce6f6eb2
[ImportVerilog]Dedup module Op (#7245)
Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
2024-07-18 10:05:44 +08:00
Amelia Dobis 815da47151
[Verif] Add formal test intent ops (#7145)
The goal of this PR is to introduce a first round of new test intent operations, for formal tests this time, to the verif dialect.

The ops that have been added in this PR are:
- verif.formal
- verif.symbolic_input
- verif.concrete_input
2024-07-17 15:47:53 -07:00
Fabian Schuiki cdc9964385
[ImportVerilog] Fix unbased unsized literals of packed aggregate type (#7336)
Fix an issue where ImportVerilog would currently crash if an unbased,
unsized literal like `'0` is used to initialize or assign to a packed
struct. Instead, the integer literal should be constructed and then
converted to the packed aggregate type. In a later pass, this conversion
can be lowered to a more careful `moore.struct_create`.
2024-07-17 15:39:54 -07:00
Fabian Schuiki 419de21c45
[ImportVerilog] Fix root op ordering
Use `upper_bound` to pick an insertion point for modules. This ensures
that multiple parametrizations of a module appear in the order in which
they were instantiated, instead of the reverse order.
2024-07-17 12:41:20 -07:00
Hideto Ueno 9845589129
[ExportVerilog] Add "context" to imported DPI functions (#7333)
This commit adds "context" property to DPI import statements to enable us to call exported functions from DPI functions. Ideally it's better to create an attribute to specify the property "context" or "pure" but "context" by default should be ok for now.
2024-07-18 03:58:47 +09:00
John Demme 08b94a7e54
[PyCDE] Bundles: coerce method (#7331)
Coerce a two-channel, bidirectional bundle to a different two-channel,
bidirectional bundle type. Transform functions can be provided to
transform the individual channels for situations where the types do not
match.
2024-07-17 08:21:12 -07:00
Leon Hielscher faa22e828e [NFC] Remove trailing whitespaces
Signed-off-by: Leon Hielscher <hielscher@fzi.de>
2024-07-17 16:35:28 +02:00
John Demme d26d288249
[PyCDE] Simple transforms on channels (#7330)
Add 'transform' method to ChannelSignals to enable simple data
manipulations without worrying about signaling.
2024-07-17 06:04:09 -07:00
fzi-hielscher 458717bc24
[Sim] Add printing operations and transformation from non-procedural to procedural flavor (#7292) 2024-07-17 14:09:59 +02:00
Mike Urbach de80eb4381
Reland "[FIRRTL][LowerClass] Pre-allocate namespaces before capturing refs (#7102)". (#7328)
This was originally added to avoid a use-after-free. However, it got
removed as part of f4920aa. It seems this is still required, even when
we process PathTrackers sequentially. I confirmed there was a
use-after-free without this change, which is fixed after adding this
back.

Closes https://github.com/llvm/circt/issues/7327.
2024-07-16 15:06:50 -06:00
fzi-hielscher 911988f8e1
[Sim] Flatten format string concatenations in canonicalizer (#7316)
Provide an interface to get the flat format string for sim.fmt.concat operations and opportunistically flatten during canonicalization.
2024-07-16 22:35:33 +02:00
Bea Healy a9ac3ae4b0
[circt-bmc] Add ExternalizeRegisters Pass (#7285)
Adds a pass to externalize register states as module inputs and outputs


Co-authored-by: Martin Erhart <maerhart@outlook.com>
2024-07-16 19:34:12 +01:00
Schuyler Eldridge ffde8abb3a
[FIRRTL] Whitespace cleanup in test, NFC
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2024-07-15 18:53:51 -04:00
Schuyler Eldridge d940c9d674
[FIRRTL] Minor cleanup in dedup, NFC
Fix two tidy warnings inside the dedup pass.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2024-07-15 18:53:01 -04:00
Schuyler Eldridge a1889207b1
[FIRRTL] Report all "must dedup" errors
Change FIRRTL's deduplication pass to report all errors arising from
modules marked "must deduplicate" that do not expectedly deduplicate.
This provides a better user experience because they do not have to iterate
on long compiles only to get "one more error".

Fixes #7324.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2024-07-15 18:48:48 -04:00
John Demme 1174c57d10 [PyCDE] Windows wheels: missing zlib1 DLL
Should fix the missing zlib1 DLL issue. Delvewheel didn't work.
2024-07-15 18:33:20 +02:00
Will Dietz 18a784a807 [FIRRTL][FIRParser][NFC] Fix warning w/o asserts, touchup. 2024-07-15 10:28:27 -05:00
Hailong Sun 4673afe1f5
[MooreToCore] Lower var, read, and assign into LLHD. (#7297) 2024-07-15 11:53:47 +08:00
Fabian Schuiki dfd4483d01
[Moore] Handle top-level typedefs by ignoring them
Typedefs are handled by Slang during type checking and don't need to be
lowered into anything in the IR. Therefore ignore top-level typedefs.
2024-07-14 11:47:03 -07:00
Lenny Truong 728a2197b3
[llvm] Bump to 0870afaaaccde5b4bae37abfc982207ffafb8332 (#7318)
* [llvm] Bump to 0870afaaaccde5b4bae37abfc982207ffafb8332

* Resolve ambiguous references

* Add include
2024-07-14 06:23:28 -07:00
Jack Koenig e9e5a6c7e9
[CI] Drop macos-11 runners, use macos-12 in uploadReleaseArtifacts (#7319) 2024-07-12 15:55:07 -07:00
Amelia Dobis 2f8ba28db8
[SV] Add Intermediary Assert Op for better enable polarity flip (#7302)
This PR introduces a new assert property op to the sv dialect and uses that as an intermediary for property assertion emission. This should solve the issue of the polarity being different in SV and in verif for the enable signals ( enable in verif, disable in sv ).
2024-07-12 10:34:04 -07:00
Jack Koenig 8bc5e93cdf
Revert "[FIRRTL] Enable Wire Elimination (#7073)" (#7311)
This reverts commit f5a0969fbe.
2024-07-12 08:51:52 -07:00
John Demme 462f6b5934
[ESI] Remove last references to capnp (#7315)
The cosim document was 90% out of date. Added a note regarding
documentation status.
2024-07-12 06:36:10 -07:00
John Demme b68c01def2
[ESI][PyCDE] ChannelSignal: add `buffer` method (#7310)
Adds a channel buffer to an ESI channel. Since the channel buffer lowers
to a SystemVerilog primitive, we need to copy the ESI primitives file
into the output dir.
2024-07-12 05:07:13 -07:00
John Demme 34263bd91f
[ESI] MMIO read service implementation in PyCDE (#7306)
Implements a channel-based MMIO read service generator. Changes the offset type on the MMIO std service to `ui32` from `i32`.
2024-07-12 05:01:41 -07:00
Robert Young cdfcd96664
Allow firrtl hardware ops under sv.ifdef (#7309) 2024-07-11 20:54:25 -04:00
Bea Healy 961bad58f4
[Verif] Add `verif.bmc` operation (#7263)
Add an op to represent bounded model checking problems
2024-07-11 18:33:36 +01:00
John Demme 595d985475 [PyCDE] Bug fixes related to indexing
- ExtractOp doesn't support i0 results.
- Didn't support negative indices.
2024-07-11 13:35:41 +00:00
John Demme a67bfb5df9 [PyCDE] Debug improvements
- Run verify-connections after each pass which allows user interactions.
- Add debug info (line numbers) to debug IR.
2024-07-11 11:56:26 +00:00
John Demme 464f177ddc [ESI] Adjustments and fixes to cosim
Only affects Questa simulation.
- Fix the build rpath so one can run Questa on the build directory.
- Remove the CXX path as it doesn't seem to be necessary any longer.
- Switch the timescale to something more reasonable.
2024-07-11 11:29:14 +00:00
John Demme 04128c51c5 [ESI] Revert ESI manifest version to 0
Version 0 means that everything is subject to change. More appropriate
for alpha builds.
2024-07-11 09:52:33 +00:00
John Demme 2ea0b031e0 [PyCDE] AssignableSignal interface
Introduce a new Python "interface" class (to make type checkers closer
to happy). It simply unifies classes which can be (and are required to
be) assigned to.
2024-07-11 09:40:22 +00:00
Will Dietz 1dfdadaf28 [HW][CAPI][NFC] Fix cast warning.
Casting from interface to operation generates these warnings,
as with other instances resolve by casting from Operation* instead.

> llvm/llvm/include/llvm/Support/Casting.h:490:69: warning: returning reference to local temporary object [-Wreturn-stack-address]
2024-07-10 15:58:03 -05:00