mirror of https://github.com/llvm/circt.git
[Sim] Add printing operations and transformation from non-procedural to procedural flavor (#7292)
This commit is contained in:
fzi-hielscher
GitHub
parent
de80eb4381
commit
458717bc24
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@ -12,3 +12,8 @@
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add_circt_dialect(Sim sim)
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add_circt_dialect_doc(Sim sim)
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add_dependencies(circt-headers MLIRSimIncGen)
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set(LLVM_TARGET_DEFINITIONS SimPasses.td)
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mlir_tablegen(SimPasses.h.inc -gen-pass-decls)
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add_public_tablegen_target(CIRCTSimTransformsIncGen)
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add_dependencies(circt-headers CIRCTSimTransformsIncGen)
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@ -29,4 +29,24 @@
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#define GET_OP_CLASSES
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#include "circt/Dialect/Sim/Sim.h.inc"
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namespace circt {
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namespace sim {
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/// Returns the value operand of a value formatting operation.
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/// Returns a null value for all other operations.
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static inline mlir::Value getFormattedValue(mlir::Operation *fmtOp) {
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if (auto fmt = llvm::dyn_cast_or_null<circt::sim::FormatBinOp>(fmtOp))
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return fmt.getValue();
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if (auto fmt = llvm::dyn_cast_or_null<circt::sim::FormatDecOp>(fmtOp))
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return fmt.getValue();
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if (auto fmt = llvm::dyn_cast_or_null<circt::sim::FormatHexOp>(fmtOp))
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return fmt.getValue();
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if (auto fmt = llvm::dyn_cast_or_null<circt::sim::FormatCharOp>(fmtOp))
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return fmt.getValue();
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return {};
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}
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} // namespace sim
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} // namespace circt
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#endif // CIRCT_DIALECT_SIM_SIMOPS_H
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@ -327,4 +327,42 @@ def FormatStringConcatOp : SimOp<"fmt.concat", [Pure]> {
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];
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}
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def PrintFormattedOp : SimOp<"print"> {
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let summary = "Print a formatted string on a given clock and condition";
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let description = [{
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Evaluate a format string and print it to the simulation console on the
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rising edge of the given clock, if, and only if, the condition argument
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is 'true'.
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Multiple print operations in the same module and on the same clock edge
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are performed according to their order of occurence in the IR. The order
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of printing for operations in different modules, instances or on different
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clocks is undefined.
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}];
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let arguments = (ins FormatStringType:$input, ClockType:$clock, I1:$condition);
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let hasCanonicalizeMethod = true;
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let assemblyFormat = "$input `on` $clock `if` $condition attr-dict";
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}
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def PrintFormattedProcOp : SimOp<"proc.print"> {
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let summary = "Print a formatted string within a procedural region";
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let description = [{
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Evaluate a format string and print it to the simulation console.
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This operation must be within a procedural region.
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}];
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let arguments = (ins FormatStringType:$input);
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let hasVerifier = true;
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let hasCanonicalizeMethod = true;
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let assemblyFormat = "$input attr-dict";
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}
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#endif // CIRCT_DIALECT_SIM_SIMOPS_TD
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@ -0,0 +1,31 @@
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//===- SimPasses.h - Sim pass entry points ----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This header file defines prototypes that expose pass constructors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CIRCT_DIALECT_SIM_SIMPASSES_H
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#define CIRCT_DIALECT_SIM_SIMPASSES_H
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#include "mlir/Pass/Pass.h"
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#include "llvm/ADT/StringRef.h"
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namespace circt {
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namespace sim {
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#define GEN_PASS_DECL
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#include "circt/Dialect/Sim/SimPasses.h.inc"
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/// Generate the code for registering passes.
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#define GEN_PASS_REGISTRATION
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#include "circt/Dialect/Sim/SimPasses.h.inc"
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} // namespace sim
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} // namespace circt
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#endif // CIRCT_DIALECT_SIM_SIMPASSES_H
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@ -0,0 +1,26 @@
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//===-- SimPasses.td - Sim pass definition file ------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains definitions for passes that work on the Sim dialect.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CIRCT_DIALECT_SIM_SEQPASSES
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#define CIRCT_DIALECT_SIM_SEQPASSES
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include "mlir/Pass/PassBase.td"
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def ProceduralizeSim : Pass<"sim-proceduralize", "hw::HWModuleOp"> {
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let summary = "Transform non-procedural to procedural operations.";
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let description = [{Transform non-procedural simulation operations with clock
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and enable to procedural operations wrapped in
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a procedural region.}];
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let dependentDialects = ["circt::hw::HWDialect, circt::seq::SeqDialect, mlir::scf::SCFDialect"];
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}
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#endif // CIRCT_DIALECT_SIM_SEQPASSES
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@ -34,6 +34,7 @@
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#include "circt/Dialect/SSP/SSPPasses.h"
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#include "circt/Dialect/SV/SVPasses.h"
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#include "circt/Dialect/Seq/SeqPasses.h"
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#include "circt/Dialect/Sim/SimPasses.h"
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#include "circt/Dialect/SystemC/SystemCPasses.h"
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#include "circt/Dialect/Verif/VerifPasses.h"
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#include "circt/Tools/circt-bmc/Passes.h"
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@ -72,6 +73,7 @@ inline void registerAllPasses() {
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ibis::registerPasses();
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hw::registerPasses();
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pipeline::registerPasses();
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sim::registerPasses();
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ssp::registerPasses();
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systemc::registerPasses();
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verif::registerPasses();
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@ -33,3 +33,5 @@ add_circt_dialect_library(CIRCTSim
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MLIRPass
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MLIRTransforms
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)
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add_subdirectory(Transforms)
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@ -13,7 +13,6 @@
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#include "circt/Dialect/Sim/SimOps.h"
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#include "circt/Dialect/HW/ModuleImplementation.h"
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#include "circt/Dialect/SV/SVOps.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/Interfaces/FunctionImplementation.h"
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@ -346,6 +345,53 @@ LogicalResult FormatStringConcatOp::canonicalize(FormatStringConcatOp op,
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return success();
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}
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LogicalResult PrintFormattedOp::canonicalize(PrintFormattedOp op,
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PatternRewriter &rewriter) {
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// Remove ops with constant false condition.
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if (auto cstCond = op.getCondition().getDefiningOp<hw::ConstantOp>()) {
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if (cstCond.getValue().isZero()) {
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rewriter.eraseOp(op);
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return success();
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}
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}
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return failure();
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}
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LogicalResult PrintFormattedProcOp::verify() {
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// Check if we know for sure that the parent is not procedural.
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auto *parentOp = getOperation()->getParentOp();
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if (!parentOp)
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return emitOpError("must be within a procedural region.");
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if (isa<hw::HWDialect>(parentOp->getDialect())) {
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if (!isa<hw::TriggeredOp>(parentOp))
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return emitOpError("must be within a procedural region.");
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return success();
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}
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if (isa<sv::SVDialect>(parentOp->getDialect())) {
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if (!parentOp->hasTrait<sv::ProceduralRegion>())
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return emitOpError("must be within a procedural region.");
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return success();
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}
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// Don't fail for dialects that are not explicitly handled.
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return success();
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}
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LogicalResult PrintFormattedProcOp::canonicalize(PrintFormattedProcOp op,
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PatternRewriter &rewriter) {
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// Remove empty prints.
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if (auto litInput = op.getInput().getDefiningOp<FormatLitOp>()) {
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if (litInput.getLiteral().empty()) {
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rewriter.eraseOp(op);
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return success();
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}
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}
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return failure();
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}
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//===----------------------------------------------------------------------===//
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// TableGen generated logic.
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//===----------------------------------------------------------------------===//
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@ -0,0 +1,19 @@
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add_circt_dialect_library(CIRCTSimTransforms
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ProceduralizeSim.cpp
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DEPENDS
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CIRCTSimTransformsIncGen
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LINK_LIBS PUBLIC
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CIRCTHW
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CIRCTSim
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CIRCTSeq
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CIRCTSV
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CIRCTComb
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CIRCTSupport
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MLIRIR
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MLIRPass
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MLIRSCFDialect
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MLIRTransformUtils
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)
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@ -0,0 +1,267 @@
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//===- ProceduralizeSim.cpp - Conversion to procedural operations ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Transform non-procedural simulation operations with clock and enable to
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// procedural operations wrapped in a procedural region.
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Dialect/HW/HWOps.h"
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#include "circt/Dialect/Seq/SeqOps.h"
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#include "circt/Dialect/Sim/SimOps.h"
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#include "circt/Dialect/Sim/SimTypes.h"
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#include "circt/Support/Debug.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/Support/Debug.h"
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#include "mlir/Dialect/SCF/IR/SCF.h"
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#include "mlir/Pass/Pass.h"
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#define DEBUG_TYPE "proceduralize-sim"
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namespace circt {
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namespace sim {
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#define GEN_PASS_DEF_PROCEDURALIZESIM
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#include "circt/Dialect/Sim/SimPasses.h.inc"
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} // namespace sim
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} // namespace circt
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using namespace llvm;
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using namespace circt;
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using namespace sim;
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namespace {
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struct ProceduralizeSimPass : impl::ProceduralizeSimBase<ProceduralizeSimPass> {
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public:
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void runOnOperation() override;
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private:
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LogicalResult proceduralizePrintOps(Value clock,
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ArrayRef<PrintFormattedOp> printOps);
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SmallVector<Operation *> getPrintTokens(PrintFormattedOp op);
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void cleanup();
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// Mapping Clock -> List of printf ops
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SmallMapVector<Value, SmallVector<PrintFormattedOp>, 2> printfOpMap;
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// List of formatting ops to be pruned after proceduralization.
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SmallVector<Operation *> cleanupList;
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};
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} // namespace
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LogicalResult ProceduralizeSimPass::proceduralizePrintOps(
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Value clock, ArrayRef<PrintFormattedOp> printOps) {
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// List of uniqued values to become arguments of the TriggeredOp.
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SmallSetVector<Value, 4> arguments;
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// Map printf ops -> flattened list of tokens
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SmallDenseMap<PrintFormattedOp, SmallVector<Operation *>, 4> tokenMap;
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SmallVector<Location> locs;
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SmallDenseSet<Value, 1> alwaysEnabledConditions;
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locs.reserve(printOps.size());
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for (auto printOp : printOps) {
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// Handle the print condition value. If it is not constant, it has to become
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// a region argument. If it is constant false, skip the operation.
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if (auto cstCond = printOp.getCondition().getDefiningOp<hw::ConstantOp>()) {
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if (cstCond.getValue().isAllOnes())
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alwaysEnabledConditions.insert(printOp.getCondition());
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else
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continue;
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} else {
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arguments.insert(printOp.getCondition());
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}
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// Accumulate locations
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locs.push_back(printOp.getLoc());
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// Get the flat list of formatting tokens and collect leaf tokens
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SmallVector<Value> flatString;
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if (auto concatInput =
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printOp.getInput().getDefiningOp<FormatStringConcatOp>()) {
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auto isAcyclic = concatInput.getFlattenedInputs(flatString);
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if (failed(isAcyclic)) {
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printOp.emitError("Cyclic format string cannot be proceduralized.");
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return failure();
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}
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} else {
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flatString.push_back(printOp.getInput());
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}
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auto &tokenList = tokenMap[printOp];
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assert(tokenList.empty() && "printf operation visited twice.");
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for (auto &token : flatString) {
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auto *fmtOp = token.getDefiningOp();
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if (!fmtOp) {
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printOp.emitError("Proceduralization of format strings passed as block "
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"argument is unsupported.");
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return failure();
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}
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tokenList.push_back(fmtOp);
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// For non-literal tokens, the value to be formatted has to become an
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// argument.
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if (!llvm::isa<FormatLitOp>(fmtOp)) {
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auto fmtVal = getFormattedValue(fmtOp);
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assert(!!fmtVal && "Unexpected foramtting token op.");
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arguments.insert(fmtVal);
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}
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}
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}
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// Build the hw::TriggeredOp
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OpBuilder builder(printOps.back());
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auto fusedLoc = builder.getFusedLoc(locs);
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SmallVector<Value> argVec = arguments.takeVector();
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auto clockConv = builder.createOrFold<seq::FromClockOp>(fusedLoc, clock);
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auto trigOp = builder.create<hw::TriggeredOp>(
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fusedLoc,
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hw::EventControlAttr::get(builder.getContext(),
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hw::EventControl::AtPosEdge),
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clockConv, argVec);
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// Map the collected arguments to the newly created block arguments.
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IRMapping argumentMapper;
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unsigned idx = 0;
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for (auto arg : argVec) {
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argumentMapper.map(arg, trigOp.getBodyBlock()->getArgument(idx));
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idx++;
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}
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// Materialize and map a 'true' constant within the TriggeredOp if required.
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builder.setInsertionPointToStart(trigOp.getBodyBlock());
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if (!alwaysEnabledConditions.empty()) {
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auto cstTrue = builder.createOrFold<hw::ConstantOp>(
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fusedLoc, IntegerAttr::get(builder.getI1Type(), 1));
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for (auto cstCond : alwaysEnabledConditions)
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argumentMapper.map(cstCond, cstTrue);
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}
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SmallDenseMap<Operation *, Operation *> cloneMap;
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Value prevConditionValue;
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Block *prevConditionBlock;
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for (auto printOp : printOps) {
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// Throw away disabled prints
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if (auto cstCond = printOp.getCondition().getDefiningOp<hw::ConstantOp>()) {
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if (cstCond.getValue().isZero()) {
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printOp.erase();
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continue;
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}
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}
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// Create a copy of the required token operations within the TriggeredOp's
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// body.
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auto tokens = tokenMap[printOp];
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SmallVector<Value> clonedOperands;
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builder.setInsertionPointToStart(trigOp.getBodyBlock());
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for (auto *token : tokens) {
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auto &fmtCloned = cloneMap[token];
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if (!fmtCloned)
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fmtCloned = builder.clone(*token, argumentMapper);
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clonedOperands.push_back(fmtCloned->getResult(0));
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}
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// Concatenate tokens to a single value if necessary.
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Value procPrintInput;
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if (clonedOperands.size() != 1)
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procPrintInput = builder.createOrFold<FormatStringConcatOp>(
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printOp.getLoc(), clonedOperands);
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else
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procPrintInput = clonedOperands.front();
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// Check if we can reuse the previous conditional block.
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auto condArg = argumentMapper.lookup(printOp.getCondition());
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if (condArg != prevConditionValue)
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prevConditionBlock = nullptr;
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auto *condBlock = prevConditionBlock;
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// If not, create a new scf::IfOp for the condition.
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if (!condBlock) {
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builder.setInsertionPointToEnd(trigOp.getBodyBlock());
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auto ifOp = builder.create<mlir::scf::IfOp>(printOp.getLoc(), TypeRange{},
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condArg, true, false);
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builder.setInsertionPointToStart(&ifOp.getThenRegion().front());
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builder.create<mlir::scf::YieldOp>(printOp.getLoc());
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condBlock = builder.getBlock();
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prevConditionValue = condArg;
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prevConditionBlock = condBlock;
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}
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// Create the procedural print operation and prune the operations outside of
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// the TriggeredOp.
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builder.setInsertionPoint(condBlock->getTerminator());
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builder.create<PrintFormattedProcOp>(printOp.getLoc(), procPrintInput);
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cleanupList.push_back(printOp.getInput().getDefiningOp());
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printOp.erase();
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}
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return success();
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}
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// Prune the DAGs of formatting tokens left outside of the newly created
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// TriggeredOps.
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void ProceduralizeSimPass::cleanup() {
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SmallVector<Operation *> cleanupNextList;
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SmallDenseSet<Operation *> erasedOps;
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bool noChange = true;
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while (!cleanupList.empty() || !cleanupNextList.empty()) {
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||||
if (cleanupList.empty()) {
|
||||
if (noChange)
|
||||
break;
|
||||
cleanupList = std::move(cleanupNextList);
|
||||
cleanupNextList = {};
|
||||
noChange = true;
|
||||
}
|
||||
|
||||
auto *opToErase = cleanupList.pop_back_val();
|
||||
if (erasedOps.contains(opToErase))
|
||||
continue;
|
||||
|
||||
if (opToErase->getUses().empty()) {
|
||||
// Remove a dead op. If it is a concat remove its operands, too.
|
||||
if (auto concat = dyn_cast<FormatStringConcatOp>(opToErase))
|
||||
for (auto operand : concat.getInputs())
|
||||
cleanupNextList.push_back(operand.getDefiningOp());
|
||||
opToErase->erase();
|
||||
erasedOps.insert(opToErase);
|
||||
noChange = false;
|
||||
} else {
|
||||
// Op still has uses, revisit later.
|
||||
cleanupNextList.push_back(opToErase);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ProceduralizeSimPass::runOnOperation() {
|
||||
LLVM_DEBUG(debugPassHeader(this) << "\n");
|
||||
printfOpMap.clear();
|
||||
cleanupList.clear();
|
||||
|
||||
auto theModule = getOperation();
|
||||
// Collect printf operations grouped by their clock.
|
||||
theModule.walk<mlir::WalkOrder::PreOrder>(
|
||||
[&](PrintFormattedOp op) { printfOpMap[op.getClock()].push_back(op); });
|
||||
|
||||
// Create a hw::TriggeredOp for each clock
|
||||
for (auto &[clock, printOps] : printfOpMap)
|
||||
if (failed(proceduralizePrintOps(clock, printOps))) {
|
||||
signalPassFailure();
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup();
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
// RUN: circt-opt --canonicalize %s | FileCheck %s
|
||||
|
||||
// CHECK-LABEL: hw.module @always_disabled
|
||||
// CHECK-NOT: sim.print
|
||||
hw.module @always_disabled(in %clock: !seq.clock) {
|
||||
%false = hw.constant false
|
||||
%lit = sim.fmt.lit "Foo"
|
||||
sim.print %lit on %clock if %false
|
||||
}
|
||||
|
||||
// CHECK-LABEL: hw.module @emtpy_proc_print
|
||||
// CHECK-NOT: sim.proc.print
|
||||
hw.module @emtpy_proc_print(in %trigger: i1) {
|
||||
hw.triggered posedge %trigger {
|
||||
%epsilon = sim.fmt.lit ""
|
||||
sim.proc.print %epsilon
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
// RUN: circt-opt --sim-proceduralize --split-input-file --verify-diagnostics %s
|
||||
|
||||
hw.module @cyclic_concat(in %clk : !seq.clock) {
|
||||
%true = hw.constant true
|
||||
%ping = sim.fmt.concat (%pong)
|
||||
%pong = sim.fmt.concat (%ping)
|
||||
// expected-error @below {{Cyclic format string cannot be proceduralized.}}
|
||||
sim.print %ping on %clk if %true
|
||||
}
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
// RUN: circt-opt --sim-proceduralize --canonicalize %s | FileCheck %s
|
||||
|
||||
// CHECK-LABEL: @basic_print1
|
||||
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
|
||||
// CHECK-NEXT: hw.triggered posedge %[[TRG]] {
|
||||
// CHECK-NEXT: %[[LIT:.*]] = sim.fmt.lit "Test"
|
||||
// CHECK-NEXT: sim.proc.print %[[LIT]]
|
||||
// CHECK-NEXT: }
|
||||
|
||||
hw.module @basic_print1(in %clk : !seq.clock) {
|
||||
%true = hw.constant true
|
||||
%test = sim.fmt.lit "Test"
|
||||
sim.print %test on %clk if %true
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @basic_print2
|
||||
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
|
||||
// CHECK-NEXT: hw.triggered posedge %[[TRG]](%cond) : i1 {
|
||||
// CHECK-NEXT: ^bb0(%[[ARG:.*]]: i1):
|
||||
// CHECK-DAG: %[[LIT1:.*]] = sim.fmt.lit "Not with a bang but a \00"
|
||||
// CHECK-DAG: %[[LIT0:.*]] = sim.fmt.lit "This is the way the world ends\0A"
|
||||
// CHECK: scf.if %[[ARG]] {
|
||||
// CHECK-NEXT: sim.proc.print %[[LIT0]]
|
||||
// CHECK-NEXT: sim.proc.print %[[LIT0]]
|
||||
// CHECK-NEXT: sim.proc.print %[[LIT0]]
|
||||
// CHECK-NEXT: sim.proc.print %[[LIT1]]
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: }
|
||||
|
||||
hw.module @basic_print2(in %clk : !seq.clock, in %cond : i1) {
|
||||
%0 = sim.fmt.lit "Not with a bang but a \00"
|
||||
%1 = sim.fmt.lit "This is the way the world ends\0A"
|
||||
|
||||
sim.print %1 on %clk if %cond
|
||||
sim.print %1 on %clk if %cond
|
||||
sim.print %1 on %clk if %cond
|
||||
sim.print %0 on %clk if %cond
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @basic_print3
|
||||
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
|
||||
// CHECK-NEXT: hw.triggered posedge %[[TRG]](%val) : i32 {
|
||||
// CHECK-NEXT: ^bb0(%[[ARG:.*]]: i32):
|
||||
// CHECK-DAG: %[[LB:.*]] = sim.fmt.lit "Bin: "
|
||||
// CHECK-DAG: %[[LD:.*]] = sim.fmt.lit ", Dec: "
|
||||
// CHECK-DAG: %[[LH:.*]] = sim.fmt.lit ", Hex: "
|
||||
// CHECK-DAG: %[[FB:.*]] = sim.fmt.bin %[[ARG]] : i32
|
||||
// CHECK-DAG: %[[FD:.*]] = sim.fmt.dec %[[ARG]] : i32
|
||||
// CHECK-DAG: %[[FH:.*]] = sim.fmt.hex %[[ARG]] : i32
|
||||
// CHECK-DAG: %[[CAT:.*]] = sim.fmt.concat (%[[LB]], %[[FB]], %[[LD]], %[[FD]], %[[LH]], %[[FH]])
|
||||
// CHECK: sim.proc.print %[[CAT]]
|
||||
// CHECK-NEXT: }
|
||||
|
||||
hw.module @basic_print3(in %clk : !seq.clock, in %val: i32) {
|
||||
%true = hw.constant true
|
||||
%comma = sim.fmt.lit ", "
|
||||
|
||||
%bin_lit = sim.fmt.lit "Bin: "
|
||||
%bin_val = sim.fmt.bin %val : i32
|
||||
%bin_cat = sim.fmt.concat (%bin_lit, %bin_val)
|
||||
|
||||
%dec_lit = sim.fmt.lit "Dec: "
|
||||
%dec_val = sim.fmt.dec %val : i32
|
||||
%dec_cat = sim.fmt.concat (%dec_lit, %dec_val)
|
||||
|
||||
%hex_lit = sim.fmt.lit "Hex: "
|
||||
%hex_val = sim.fmt.hex %val : i32
|
||||
%hex_cat = sim.fmt.concat (%hex_lit, %hex_val)
|
||||
|
||||
%str = sim.fmt.concat (%bin_cat, %comma, %dec_cat, %comma, %hex_cat)
|
||||
|
||||
sim.print %str on %clk if %true
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @multi_args
|
||||
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
|
||||
// CHECK-NEXT: hw.triggered posedge %0(%a, %b, %c) : i8, i8, i8 {
|
||||
// CHECK-NEXT: ^bb0(%[[ARG0:.*]]: i8, %[[ARG1:.*]]: i8, %[[ARG2:.*]]: i8):
|
||||
// CHECK-DAG: %[[COM:.*]] = sim.fmt.lit ", "
|
||||
// CHECK-DAG: %[[B0:.*]] = sim.fmt.bin %[[ARG0]] : i8
|
||||
// CHECK-DAG: %[[H0:.*]] = sim.fmt.hex %[[ARG0]] : i8
|
||||
// CHECK-DAG: %[[B1:.*]] = sim.fmt.bin %[[ARG1]] : i8
|
||||
// CHECK-DAG: %[[H1:.*]] = sim.fmt.hex %[[ARG1]] : i8
|
||||
// CHECK-DAG: %[[B2:.*]] = sim.fmt.bin %[[ARG2]] : i8
|
||||
// CHECK-DAG: %[[H2:.*]] = sim.fmt.hex %[[ARG2]] : i8
|
||||
// CHECK-DAG: %[[CAT:.*]] = sim.fmt.concat (%[[B0]], %[[B1]], %[[B2]], %[[COM]], %[[H0]], %[[H1]], %[[H2]])
|
||||
// CHECK: sim.proc.print %[[CAT]]
|
||||
// CHECK-NEXT: }
|
||||
|
||||
hw.module @multi_args(in %clk : !seq.clock, in %a: i8, in %b: i8, in %c: i8) {
|
||||
%true = hw.constant true
|
||||
%comma = sim.fmt.lit ", "
|
||||
|
||||
%bina = sim.fmt.bin %a : i8
|
||||
%binb = sim.fmt.bin %b : i8
|
||||
%binc = sim.fmt.bin %c : i8
|
||||
|
||||
%hexa = sim.fmt.hex %a : i8
|
||||
%hexb = sim.fmt.hex %b : i8
|
||||
%hexc = sim.fmt.hex %c : i8
|
||||
|
||||
%cat = sim.fmt.concat (%bina, %binb, %binc, %comma, %hexa, %hexb, %hexc)
|
||||
|
||||
sim.print %cat on %clk if %true
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @multi_clock
|
||||
// CHECK-NEXT: %[[TRGA:.*]] = seq.from_clock %clka
|
||||
// CHECK-NEXT: hw.triggered posedge %[[TRGA]](%val) : i32 {
|
||||
// CHECK-NEXT: ^bb0(%[[ARGA:.*]]: i32):
|
||||
// CHECK-DAG: %[[LA0:.*]] = sim.fmt.lit "Val is 0x"
|
||||
// CHECK-DAG: %[[LA1:.*]] = sim.fmt.lit " on A."
|
||||
// CHECK-DAG: %[[FA:.*]] = sim.fmt.hex %[[ARGA]] : i32
|
||||
// CHECK-DAG: %[[CATA:.*]] = sim.fmt.concat (%[[LA0]], %[[FA]], %[[LA1]])
|
||||
// CHECK: sim.proc.print %[[CATA]]
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: %[[TRGB:.*]] = seq.from_clock %clkb
|
||||
// CHECK-NEXT: hw.triggered posedge %[[TRGB]](%val) : i32 {
|
||||
// CHECK-NEXT: ^bb0(%[[ARGB:.*]]: i32):
|
||||
// CHECK-DAG: %[[LB0:.*]] = sim.fmt.lit "Val is 0x"
|
||||
// CHECK-DAG: %[[LB1:.*]] = sim.fmt.lit " on B."
|
||||
// CHECK-DAG: %[[FB:.*]] = sim.fmt.hex %[[ARGB]] : i32
|
||||
// CHECK-DAG: %[[CATB:.*]] = sim.fmt.concat (%[[LB0]], %[[FB]], %[[LB1]])
|
||||
// CHECK: sim.proc.print %[[CATB]]
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: %[[TRGC:.*]] = seq.from_clock %clkc
|
||||
// CHECK-NEXT: hw.triggered posedge %[[TRGC]](%val) : i32 {
|
||||
// CHECK-NEXT: ^bb0(%[[ARGC:.*]]: i32):
|
||||
// CHECK-DAG: %[[LC0:.*]] = sim.fmt.lit "Val is 0x"
|
||||
// CHECK-DAG: %[[LC1:.*]] = sim.fmt.lit " on C."
|
||||
// CHECK-DAG: %[[FC:.*]] = sim.fmt.hex %[[ARGC]] : i32
|
||||
// CHECK-DAG: %[[CATC:.*]] = sim.fmt.concat (%[[LC0]], %[[FC]], %[[LC1]])
|
||||
// CHECK: sim.proc.print %[[CATC]]
|
||||
// CHECK-NEXT: }
|
||||
|
||||
hw.module @multi_clock(in %clka : !seq.clock, in %clkb : !seq.clock, in %clkc : !seq.clock, in %val: i32) {
|
||||
%true = hw.constant true
|
||||
%pre = sim.fmt.lit "Val is 0x"
|
||||
%hex_val = sim.fmt.hex %val : i32
|
||||
|
||||
%onA = sim.fmt.lit " on A."
|
||||
%onB = sim.fmt.lit " on B."
|
||||
%onC = sim.fmt.lit " on C."
|
||||
|
||||
%catA = sim.fmt.concat (%pre, %hex_val, %onA)
|
||||
sim.print %catA on %clka if %true
|
||||
|
||||
%catB = sim.fmt.concat (%pre, %hex_val, %onB)
|
||||
sim.print %catB on %clkb if %true
|
||||
|
||||
%catC = sim.fmt.concat (%pre, %hex_val, %onC)
|
||||
sim.print %catC on %clkc if %true
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @sequence
|
||||
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
|
||||
// CHECK-NEXT: hw.triggered posedge %[[TRG]](%conda, %condb, %val) : i1, i1, i32 {
|
||||
// CHECK-NEXT: ^bb0(%[[ARG0:.*]]: i1, %[[ARG1:.*]]: i1, %[[ARG2:.*]]: i32):
|
||||
// CHECK-DAG: %[[L1:.*]] = sim.fmt.lit "#1"
|
||||
// CHECK-DAG: %[[L2:.*]] = sim.fmt.lit "#2"
|
||||
// CHECK-DAG: %[[L3:.*]] = sim.fmt.lit "#3"
|
||||
// CHECK-DAG: %[[L4:.*]] = sim.fmt.lit "#4"
|
||||
// CHECK-DAG: %[[L5:.*]] = sim.fmt.lit "#5"
|
||||
// CHECK-DAG: %[[L6:.*]] = sim.fmt.lit "#6"
|
||||
// CHECK-DAG: %[[BIN:.*]] = sim.fmt.bin %[[ARG2]] : i32
|
||||
// CHECK: scf.if %[[ARG0]] {
|
||||
// CHECK-NEXT: sim.proc.print %[[L1]]
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: scf.if %[[ARG1]] {
|
||||
// CHECK-NEXT: sim.proc.print %[[L2]]
|
||||
// CHECK-NEXT: sim.proc.print %[[L3]]
|
||||
// CHECK-NEXT: sim.proc.print %[[L4]]
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: scf.if %[[ARG0]] {
|
||||
// CHECK-NEXT: sim.proc.print %[[L5]]
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: sim.proc.print %[[BIN]]
|
||||
// CHECK-NEXT: scf.if %[[ARG0]] {
|
||||
// CHECK-NEXT: sim.proc.print %[[L6]]
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: }
|
||||
|
||||
hw.module @sequence(in %clk: !seq.clock, in %conda: i1, in %condb: i1, in %val : i32) {
|
||||
%true = hw.constant true
|
||||
%false = hw.constant false
|
||||
|
||||
%1 = sim.fmt.lit "#1"
|
||||
sim.print %1 on %clk if %conda
|
||||
%2 = sim.fmt.lit "#2"
|
||||
sim.print %2 on %clk if %condb
|
||||
%3 = sim.fmt.lit "#3"
|
||||
sim.print %3 on %clk if %condb
|
||||
%cdis = sim.fmt.lit "--"
|
||||
sim.print %cdis on %clk if %false
|
||||
%4 = sim.fmt.lit "#4"
|
||||
sim.print %4 on %clk if %condb
|
||||
%5 = sim.fmt.lit "#5"
|
||||
sim.print %5 on %clk if %conda
|
||||
%cen = sim.fmt.bin %val : i32
|
||||
sim.print %cen on %clk if %true
|
||||
%6 = sim.fmt.lit "#6"
|
||||
sim.print %6 on %clk if %conda
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @condition_as_val
|
||||
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
|
||||
// CHECK-NEXT: hw.triggered posedge %[[TRG]](%condval) : i1 {
|
||||
// CHECK-NEXT: ^bb0(%[[ARG:.*]]: i1):
|
||||
// CHECK-NEXT: %[[BIN:.*]] = sim.fmt.bin %[[ARG]] : i1
|
||||
// CHECK-NEXT: scf.if %[[ARG]] {
|
||||
// CHECK-NEXT: sim.proc.print %[[BIN]]
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: }
|
||||
|
||||
hw.module @condition_as_val(in %clk: !seq.clock, in %condval: i1) {
|
||||
%bin = sim.fmt.bin %condval : i1
|
||||
sim.print %bin on %clk if %condval
|
||||
}
|
||||
|
|
@ -23,3 +23,22 @@ hw.module @fmt_infinite_concat_canonicalize(in %val : i8, out res: !sim.fstring)
|
|||
%cat = sim.fmt.concat (%4, %c, %5)
|
||||
hw.output %cat : !sim.fstring
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
hw.module @proc_print_hw() {
|
||||
%lit = sim.fmt.lit "Nope"
|
||||
// expected-error @below {{must be within a procedural region.}}
|
||||
sim.proc.print %lit
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
sv.macro.decl @SOMEMACRO
|
||||
hw.module @proc_print_sv() {
|
||||
%lit = sim.fmt.lit "Nope"
|
||||
sv.ifdef @SOMEMACRO {
|
||||
// expected-error @below {{must be within a procedural region.}}
|
||||
sim.proc.print %lit
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ target_link_libraries(circt-opt
|
|||
CIRCTSeqToSV
|
||||
CIRCTSeqTransforms
|
||||
CIRCTSimToSV
|
||||
CIRCTSimTransforms
|
||||
CIRCTSSP
|
||||
CIRCTSSPTransforms
|
||||
CIRCTCFToHandshake
|
||||
|
|
|
|||
Loading…
Reference in New Issue