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[integration_test] Update golden verilog (#858) 

* Update the golden verilog with the latest firrtl
* firrtl output for neg, for signed and unsigned operand must respect the sign.
* This should fix the yosys integration_test failure https://github.com/llvm/circt/issues/842
* The firrtl bug fix that updates the golden: 49b8232447
This commit is contained in:
Prithayan Barua 2021-03-31 10:39:49 -07:00 committed by GitHub
parent a18efe7638
commit e9c90ae54a
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1 changed files with 2 additions and 2 deletions
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integration_test/EmitVerilog/verilog_equiv.fir
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@ -131,8 +131,8 @@ module test_unary(
assign out_head_s = sin4[3:2];
assign out_tail_u = uin4[1:0];
assign out_tail_s = sin4[1:0];
assign out_neg_u = -$signed(uin4);
assign out_neg_s = -$signed(sin4);
assign out_neg_s = 4'sh0 - $signed(sin4);
assign out_neg_u = 4'h0 - uin4;
endmodule
;--- test_prim.fir