mirror of https://github.com/llvm/circt.git
[PyCDE] Simple transforms on channels (#7330)
Add 'transform' method to ChannelSignals to enable simple data manipulations without worrying about signaling.
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@ -13,7 +13,7 @@ from .circt import ir
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from contextvars import ContextVar
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from functools import singledispatchmethod
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from typing import Dict, List, Optional, Tuple, Union
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from typing import Callable, Dict, List, Optional, Tuple, Union
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import re
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import numpy as np
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@ -736,6 +736,20 @@ class ChannelSignal(Signal):
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stages=stages,
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), self.type)
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def transform(self, transform: Callable[[Signal], Signal]) -> ChannelSignal:
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"""Transform the data in the channel using the provided function. Said
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function must be combinational so it is intended for wire and simple type
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transformations."""
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from .constructs import Wire
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from .types import Bits, Channel
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ready_wire = Wire(Bits(1))
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data, valid = self.unwrap(ready_wire)
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data = transform(data)
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ret_chan, ready = Channel(data.type).wrap(data, valid)
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ready_wire.assign(ready)
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return ret_chan
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class BundleSignal(Signal):
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"""Signal for types.Bundle."""
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@ -184,6 +184,21 @@ class RecvBundleTest(Module):
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self.s1_out = to_channels['req']
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# CHECK-LABEL: hw.module @ChannelTransform(in %s1_in : !esi.channel<i32>, out s2_out : !esi.channel<i8>) attributes {output_file = #hw.output_file<"ChannelTransform.sv", includeReplicatedOps>} {
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# CHECK-NEXT: %rawOutput, %valid = esi.unwrap.vr %s1_in, %ready : i32
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# CHECK-NEXT: [[R0:%.+]] = comb.extract %rawOutput from 0 : (i32) -> i8
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# CHECK-NEXT: %chanOutput, %ready = esi.wrap.vr [[R0]], %valid : i8
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# CHECK-NEXT: hw.output %chanOutput : !esi.channel<i8>
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@unittestmodule()
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class ChannelTransform(Module):
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s1_in = InputChannel(Bits(32))
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s2_out = OutputChannel(Bits(8))
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@generator
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def build(self):
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self.s2_out = self.s1_in.transform(lambda x: x[0:8])
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# CHECK-LABEL: hw.module @MMIOReq()
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# CHECK-NEXT: %c0_i64 = hw.constant 0 : i64
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# CHECK-NEXT: %false = hw.constant false
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