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circt/test/CAPI/CMakeLists.txt

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Create a minimal C API (#196) * Enable cloning llvm submodule over HTTP * Introduce C API * Undo unrelated changes * clang-format * More format * Add Header Comments * Format * Add basic test * Add missing incantation * Format Co-authored-by: George <>
2020-11-05 03:37:51 +08:00
add_llvm_executable(circt-capi-ir-test
ir.c
[PyCDE,CAPI] Add support for the FSM dialect (#3400) This is an initial commit for adding a CAPI for FSM as well as PyCDE support for constructing these. See `test_fsm.py` for usage. FSMs are constructed in a similar manner to PyCDE modules through a decorator on a class describing the FSM. The FSM class may contain inputs (no outputs for now) and must provide - A dictionary containing the states and their transitions - A default state State transitions may be either always taken, or taken based on some guard. This guard is defined by a function provided to the transition, which (like `@generator` functions) acts on the ports of the FSM. The FSM will then be constructed with an output for each state, asserted when that state is active. One important implementation note is the fact that the `fsm.machine` operation is treated as a PyCDE Module - there was surprisingly little friction slotting it into the current code and everything works as expected wrt. referencing `fsm.machine` in/out arguments through the transition guard functions. However, modules instantiating the FSM expect a hardware-like interface, this being the ports of the `fsm.machine` operation + clock and reset signals. An `fsm.machine` op does not have these signals at the top level, since these are added during hardware lowering. To me, this is a sensible design choice, seeing that the FSM dialect should be applicable to both software and hardware representations (...eventually). To get around this, the user will specify the intended name of the `clock` and optional `reset` signal of an FSM. A wrapper module is then created that provides the correct interface to the instantiating module, as well as instantiating the FSM through a `fsm.hw_instance` operation, doing the proper hoop-jumping to attach the clock signal (see `fsm_wrapper_class`). There's still some work to do on the CIRCT side of the FSM dialect to clean it up a bit + make it a viable target for a front-end, but this commit represents the brunt of work on the PyCDE side.
2022-06-27 22:14:38 +08:00
)
Create a minimal C API (#196) * Enable cloning llvm submodule over HTTP * Introduce C API * Undo unrelated changes * clang-format * More format * Add Header Comments * Format * Add basic test * Add missing incantation * Format Co-authored-by: George <>
2020-11-05 03:37:51 +08:00
llvm_update_compile_flags(circt-capi-ir-test)
target_link_libraries(circt-capi-ir-test
PRIVATE
Windows builds (#374) * Adding Windows build and test workflow * ubuntu -> windows * cmake paths * Adding build parallelism * Builds locally * A large portion of the tests fail on Windows * Remove release build * Debug takes up waayyy too much space! * Run in Release mode * Add '-j 1' to disable parallelism * Build LLVM separately * Fixing build workflow * Finally working! * Update buildAndTestWindows.yml Only cache object dirs * Update buildAndTestWindows.yml Fixing formatting issue * Remove pre-build job
2021-01-13 13:35:12 +08:00
Bind more API to C (#705)
2021-03-03 01:38:29 +08:00
CIRCTCAPIComb
[RTL->HW] Rename the string "RTL" to "HW" This makes sure not to rename FIRRTL to HWRTL :-), and I spot checked a many things to avoid changing general references to RTL (e.g. when referring to external tools) but I suspect that I missed some. Please let me know (or directly correct) any mistakes in this mechanical patch.
2021-05-16 03:44:05 +08:00
CIRCTCAPIHW
[Seq] Add C API for Seq dialect and pass registration. (#1006)
2021-05-05 09:06:12 +08:00
CIRCTCAPISeq
[ExportVerilog][SV] C API (#481) Co-authored-by: George <989903+GeorgeLyon@users.noreply.github.com>
2021-01-21 07:42:02 +08:00
CIRCTCAPISV
[PyCDE,CAPI] Add support for the FSM dialect (#3400) This is an initial commit for adding a CAPI for FSM as well as PyCDE support for constructing these. See `test_fsm.py` for usage. FSMs are constructed in a similar manner to PyCDE modules through a decorator on a class describing the FSM. The FSM class may contain inputs (no outputs for now) and must provide - A dictionary containing the states and their transitions - A default state State transitions may be either always taken, or taken based on some guard. This guard is defined by a function provided to the transition, which (like `@generator` functions) acts on the ports of the FSM. The FSM will then be constructed with an output for each state, asserted when that state is active. One important implementation note is the fact that the `fsm.machine` operation is treated as a PyCDE Module - there was surprisingly little friction slotting it into the current code and everything works as expected wrt. referencing `fsm.machine` in/out arguments through the transition guard functions. However, modules instantiating the FSM expect a hardware-like interface, this being the ports of the `fsm.machine` operation + clock and reset signals. An `fsm.machine` op does not have these signals at the top level, since these are added during hardware lowering. To me, this is a sensible design choice, seeing that the FSM dialect should be applicable to both software and hardware representations (...eventually). To get around this, the user will specify the intended name of the `clock` and optional `reset` signal of an FSM. A wrapper module is then created that provides the correct interface to the instantiating module, as well as instantiating the FSM through a `fsm.hw_instance` operation, doing the proper hoop-jumping to attach the clock signal (see `fsm_wrapper_class`). There's still some work to do on the CIRCT side of the FSM dialect to clean it up a bit + make it a viable target for a front-end, but this commit represents the brunt of work on the PyCDE side.
2022-06-27 22:14:38 +08:00
CIRCTCAPIFSM
[ExportVerilog][SV] C API (#481) Co-authored-by: George <989903+GeorgeLyon@users.noreply.github.com>
2021-01-21 07:42:02 +08:00
CIRCTCAPIExportVerilog
[PyCDE,CAPI] Add support for the FSM dialect (#3400) This is an initial commit for adding a CAPI for FSM as well as PyCDE support for constructing these. See `test_fsm.py` for usage. FSMs are constructed in a similar manner to PyCDE modules through a decorator on a class describing the FSM. The FSM class may contain inputs (no outputs for now) and must provide - A dictionary containing the states and their transitions - A default state State transitions may be either always taken, or taken based on some guard. This guard is defined by a function provided to the transition, which (like `@generator` functions) acts on the ports of the FSM. The FSM will then be constructed with an output for each state, asserted when that state is active. One important implementation note is the fact that the `fsm.machine` operation is treated as a PyCDE Module - there was surprisingly little friction slotting it into the current code and everything works as expected wrt. referencing `fsm.machine` in/out arguments through the transition guard functions. However, modules instantiating the FSM expect a hardware-like interface, this being the ports of the `fsm.machine` operation + clock and reset signals. An `fsm.machine` op does not have these signals at the top level, since these are added during hardware lowering. To me, this is a sensible design choice, seeing that the FSM dialect should be applicable to both software and hardware representations (...eventually). To get around this, the user will specify the intended name of the `clock` and optional `reset` signal of an FSM. A wrapper module is then created that provides the correct interface to the instantiating module, as well as instantiating the FSM through a `fsm.hw_instance` operation, doing the proper hoop-jumping to attach the clock signal (see `fsm_wrapper_class`). There's still some work to do on the CIRCT side of the FSM dialect to clean it up a bit + make it a viable target for a front-end, but this commit represents the brunt of work on the PyCDE side.
2022-06-27 22:14:38 +08:00
)