454 lines
14 KiB
C
454 lines
14 KiB
C
/* sim-fast.c - sample fast functional simulator implementation */
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/* SimpleScalar(TM) Tool Suite
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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* All Rights Reserved.
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*
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* THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
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* YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
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*
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* No portion of this work may be used by any commercial entity, or for any
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* commercial purpose, without the prior, written permission of SimpleScalar,
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* LLC (info@simplescalar.com). Nonprofit and noncommercial use is permitted
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* as described below.
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*
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* 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
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* or implied. The user of the program accepts full responsibility for the
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* application of the program and the use of any results.
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*
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* 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
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* downloaded, compiled, executed, copied, and modified solely for nonprofit,
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* educational, noncommercial research, and noncommercial scholarship
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* purposes provided that this notice in its entirety accompanies all copies.
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* Copies of the modified software can be delivered to persons who use it
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* solely for nonprofit, educational, noncommercial research, and
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* noncommercial scholarship purposes provided that this notice in its
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* entirety accompanies all copies.
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*
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* 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
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* PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC (info@simplescalar.com).
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*
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* 4. No nonprofit user may place any restrictions on the use of this software,
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* including as modified by the user, by any other authorized user.
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*
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* 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
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* in compiled or executable form as set forth in Section 2, provided that
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* either: (A) it is accompanied by the corresponding machine-readable source
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* code, or (B) it is accompanied by a written offer, with no time limit, to
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* give anyone a machine-readable copy of the corresponding source code in
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* return for reimbursement of the cost of distribution. This written offer
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* must permit verbatim duplication by anyone, or (C) it is distributed by
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* someone who received only the executable form, and is accompanied by a
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* copy of the written offer of source code.
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*
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* 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
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* currently maintained by SimpleScalar LLC (info@simplescalar.com). US Mail:
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* 2395 Timbercrest Court, Ann Arbor, MI 48105.
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*
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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/*
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* This file implements a very fast functional simulator. This functional
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* simulator implementation is much more difficult to digest than the simpler,
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* cleaner sim-safe functional simulator. By default, this simulator performs
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* no instruction error checking, as a result, any instruction errors will
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* manifest as simulator execution errors, possibly causing sim-fast to
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* execute incorrectly or dump core. Such is the price we pay for speed!!!!
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*
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* The following options configure the bag of tricks used to make sim-fast
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* live up to its name. For most machines, defining all the options results
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* in the fastest functional simulator.
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*/
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/* don't count instructions flag, enabled by default, disable for inst count */
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#undef NO_INSN_COUNT
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#ifdef __GNUC__
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/* faster dispatch mechanism, requires GNU GCC C extensions, CAVEAT: some
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versions of GNU GCC core dump when optimizing the jump table code with
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optimization levels higher than -O1 */
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/* #define USE_JUMP_TABLE */
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#endif /* __GNUC__ */
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#include "host.h"
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#include "misc.h"
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#include "machine.h"
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#include "regs.h"
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#include "memory.h"
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#include "loader.h"
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#include "syscall.h"
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#include "dlite.h"
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#include "sim.h"
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/* simulated registers */
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static struct regs_t regs;
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/* simulated memory */
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static struct mem_t *mem = NULL;
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#ifdef TARGET_ALPHA
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/* predecoded text memory */
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static struct mem_t *dec = NULL;
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#endif
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/* register simulator-specific options */
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void
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sim_reg_options(struct opt_odb_t *odb)
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{
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opt_reg_header(odb,
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"sim-fast: This simulator implements a very fast functional simulator. This\n"
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"functional simulator implementation is much more difficult to digest than\n"
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"the simpler, cleaner sim-safe functional simulator. By default, this\n"
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"simulator performs no instruction error checking, as a result, any\n"
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"instruction errors will manifest as simulator execution errors, possibly\n"
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"causing sim-fast to execute incorrectly or dump core. Such is the\n"
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"price we pay for speed!!!!\n"
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);
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}
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/* check simulator-specific option values */
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void
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sim_check_options(struct opt_odb_t *odb, int argc, char **argv)
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{
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if (dlite_active)
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fatal("sim-fast does not support DLite debugging");
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}
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/* register simulator-specific statistics */
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void
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sim_reg_stats(struct stat_sdb_t *sdb)
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{
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#ifndef NO_INSN_COUNT
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stat_reg_counter(sdb, "sim_num_insn",
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"total number of instructions executed",
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&sim_num_insn, sim_num_insn, NULL);
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#endif /* !NO_INSN_COUNT */
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stat_reg_int(sdb, "sim_elapsed_time",
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"total simulation time in seconds",
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&sim_elapsed_time, 0, NULL);
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#ifndef NO_INSN_COUNT
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stat_reg_formula(sdb, "sim_inst_rate",
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"simulation speed (in insts/sec)",
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"sim_num_insn / sim_elapsed_time", NULL);
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#endif /* !NO_INSN_COUNT */
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ld_reg_stats(sdb);
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mem_reg_stats(mem, sdb);
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#ifdef TARGET_ALPHA
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mem_reg_stats(dec, sdb);
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#endif
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}
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/* initialize the simulator */
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void
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sim_init(void)
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{
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/* allocate and initialize register file */
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regs_init(®s);
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/* allocate and initialize memory space */
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mem = mem_create("mem");
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mem_init(mem);
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}
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/* load program into simulated state */
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void
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sim_load_prog(char *fname, /* program to load */
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int argc, char **argv, /* program arguments */
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char **envp) /* program environment */
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{
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/* load program text and data, set up environment, memory, and regs */
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ld_load_prog(fname, argc, argv, envp, ®s, mem, TRUE);
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#ifdef TARGET_ALPHA
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/* pre-decode text segment */
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{
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unsigned i, num_insn = (ld_text_size + 3) / 4;
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fprintf(stderr, "** pre-decoding %u insts...", num_insn);
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/* allocate decoded text space */
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dec = mem_create("dec");
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for (i=0; i < num_insn; i++)
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{
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enum md_opcode op;
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md_inst_t inst;
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md_addr_t PC;
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/* compute PC */
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PC = ld_text_base + i * sizeof(md_inst_t);
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/* get instruction from memory */
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MD_FETCH_INST(inst, mem, PC);
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/* decode the instruction */
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MD_SET_OPCODE(op, inst);
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/* insert into decoded opcode space */
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MEM_WRITE_WORD(dec, PC << 1, (word_t)op);
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MEM_WRITE_WORD(dec, (PC << 1)+sizeof(word_t), inst);
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}
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fprintf(stderr, "done\n");
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}
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#endif /* TARGET_ALPHA */
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}
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/* print simulator-specific configuration information */
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void
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sim_aux_config(FILE *stream)
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{
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/* nothing currently */
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}
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/* dump simulator-specific auxiliary simulator statistics */
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void
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sim_aux_stats(FILE *stream)
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{
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/* nada */
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}
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/* un-initialize simulator-specific state */
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void
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sim_uninit(void)
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{
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/* nada */
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}
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/*
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* configure the execution engine
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*/
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/* next program counter */
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#define SET_NPC(EXPR) (regs.regs_NPC = (EXPR))
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/* current program counter */
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#define CPC (regs.regs_PC)
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/* general purpose registers */
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#define GPR(N) (regs.regs_R[N])
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#define SET_GPR(N,EXPR) (regs.regs_R[N] = (EXPR))
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#if defined(TARGET_PISA)
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/* floating point registers, L->word, F->single-prec, D->double-prec */
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#define FPR_L(N) (regs.regs_F.l[(N)])
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#define SET_FPR_L(N,EXPR) (regs.regs_F.l[(N)] = (EXPR))
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#define FPR_F(N) (regs.regs_F.f[(N)])
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#define SET_FPR_F(N,EXPR) (regs.regs_F.f[(N)] = (EXPR))
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#define FPR_D(N) (regs.regs_F.d[(N) >> 1])
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#define SET_FPR_D(N,EXPR) (regs.regs_F.d[(N) >> 1] = (EXPR))
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/* miscellaneous register accessors */
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#define SET_HI(EXPR) (regs.regs_C.hi = (EXPR))
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#define HI (regs.regs_C.hi)
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#define SET_LO(EXPR) (regs.regs_C.lo = (EXPR))
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#define LO (regs.regs_C.lo)
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#define FCC (regs.regs_C.fcc)
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#define SET_FCC(EXPR) (regs.regs_C.fcc = (EXPR))
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#elif defined(TARGET_ALPHA)
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/* floating point registers, L->word, F->single-prec, D->double-prec */
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#define FPR_Q(N) (regs.regs_F.q[N])
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#define SET_FPR_Q(N,EXPR) (regs.regs_F.q[N] = (EXPR))
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#define FPR(N) (regs.regs_F.d[N])
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#define SET_FPR(N,EXPR) (regs.regs_F.d[N] = (EXPR))
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/* miscellaneous register accessors */
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#define FPCR (regs.regs_C.fpcr)
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#define SET_FPCR(EXPR) (regs.regs_C.fpcr = (EXPR))
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#define UNIQ (regs.regs_C.uniq)
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#define SET_UNIQ(EXPR) (regs.regs_C.uniq = (EXPR))
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#else
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#error No ISA target defined...
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#endif
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/* precise architected memory state accessor macros */
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#define READ_BYTE(SRC, FAULT) \
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((FAULT) = md_fault_none, MEM_READ_BYTE(mem, (SRC)))
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#define READ_HALF(SRC, FAULT) \
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((FAULT) = md_fault_none, MEM_READ_HALF(mem, (SRC)))
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#define READ_WORD(SRC, FAULT) \
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((FAULT) = md_fault_none, MEM_READ_WORD(mem, (SRC)))
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#ifdef HOST_HAS_QWORD
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#define READ_QWORD(SRC, FAULT) \
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((FAULT) = md_fault_none, MEM_READ_QWORD(mem, (SRC)))
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#endif /* HOST_HAS_QWORD */
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#define WRITE_BYTE(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, MEM_WRITE_BYTE(mem, (DST), (SRC)))
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#define WRITE_HALF(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, MEM_WRITE_HALF(mem, (DST), (SRC)))
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#define WRITE_WORD(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, MEM_WRITE_WORD(mem, (DST), (SRC)))
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#ifdef HOST_HAS_QWORD
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#define WRITE_QWORD(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, MEM_WRITE_QWORD(mem, (DST), (SRC)))
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#endif /* HOST_HAS_QWORD */
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/* system call handler macro */
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#define SYSCALL(INST) sys_syscall(®s, mem_access, mem, INST, TRUE)
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#ifndef NO_INSN_COUNT
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#define INC_INSN_CTR() sim_num_insn++
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#else /* !NO_INSN_COUNT */
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#define INC_INSN_CTR() /* nada */
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#endif /* NO_INSN_COUNT */
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#ifdef TARGET_ALPHA
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#define ZERO_FP_REG() regs.regs_F.d[MD_REG_ZERO] = 0.0
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#else
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#define ZERO_FP_REG() /* nada... */
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#endif
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/* start simulation, program loaded, processor precise state initialized */
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void
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sim_main(void)
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{
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#ifdef USE_JUMP_TABLE
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/* the jump table employs GNU GCC label extensions to construct an array
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of pointers to instruction implementation code, the simulator then uses
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the table to lookup the location of instruction's implementing code, a
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GNU GCC `goto' extension is then used to jump to the inst's implementing
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code through the op_jump table; as a result, there is no need for
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a main simulator loop, which eliminates one branch from the simulator
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interpreter - crazy, no!?!? */
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/* instruction jump table, this code is GNU GCC specific */
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static void *op_jump[/* max opcodes */] = {
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&&opcode_NA, /* NA */
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#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
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&&opcode_##OP,
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#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
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&&opcode_##OP,
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#define CONNECT(OP)
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#include "machine.def"
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};
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#endif /* USE_JUMP_TABLE */
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/* register allocate instruction buffer */
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register md_inst_t inst;
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/* decoded opcode */
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register enum md_opcode op;
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fprintf(stderr, "sim: ** starting *fast* functional simulation **\n");
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/* must have natural byte/word ordering */
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if (sim_swap_bytes || sim_swap_words)
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fatal("sim: *fast* functional simulation cannot swap bytes or words");
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#ifdef USE_JUMP_TABLE
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regs.regs_NPC = regs.regs_PC;
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/* load instruction */
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MD_FETCH_INST(inst, mem, regs.regs_NPC);
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/* jump to instruction implementation */
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MD_SET_OPCODE(op, inst);
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goto *op_jump[op];
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#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
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opcode_##OP: \
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/* maintain $r0 semantics */ \
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regs.regs_R[MD_REG_ZERO] = 0; \
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ZERO_FP_REG(); \
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\
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/* keep an instruction count */ \
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INC_INSN_CTR(); \
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\
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/* locate next instruction */ \
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regs.regs_PC = regs.regs_NPC; \
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\
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/* set up default next PC */ \
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regs.regs_NPC += sizeof(md_inst_t); \
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\
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/* execute the instruction */ \
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SYMCAT(OP,_IMPL); \
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\
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/* get the next instruction */ \
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MD_FETCH_INST(inst, mem, regs.regs_NPC); \
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\
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/* jump to instruction implementation */ \
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MD_SET_OPCODE(op, inst); \
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goto *op_jump[op];
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#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
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opcode_##OP: \
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panic("attempted to execute a linking opcode");
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#define CONNECT(OP)
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#define DECLARE_FAULT(FAULT) \
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{ /* uncaught... */break; }
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#include "machine.def"
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opcode_NA:
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panic("attempted to execute a bogus opcode");
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/* should not get here... */
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panic("exited sim-fast main loop");
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#else /* !USE_JUMP_TABLE */
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/* set up initial default next PC */
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regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
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while (TRUE)
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{
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/* maintain $r0 semantics */
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regs.regs_R[MD_REG_ZERO] = 0;
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#ifdef TARGET_ALPHA
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regs.regs_F.d[MD_REG_ZERO] = 0.0;
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#endif /* TARGET_ALPHA */
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/* keep an instruction count */
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#ifndef NO_INSN_COUNT
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sim_num_insn++;
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#endif /* !NO_INSN_COUNT */
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#ifdef TARGET_ALPHA
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/* load predecoded instruction */
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op = (enum md_opcode)__UNCHK_MEM_READ(dec, regs.regs_PC << 1, word_t);
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inst =
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__UNCHK_MEM_READ(dec, (regs.regs_PC << 1)+sizeof(word_t), md_inst_t);
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#else /* !TARGET_ALPHA */
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/* load instruction */
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MD_FETCH_INST(inst, mem, regs.regs_PC);
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/* decode the instruction */
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MD_SET_OPCODE(op, inst);
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#endif
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/* execute the instruction */
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switch (op)
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{
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#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
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case OP: \
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SYMCAT(OP,_IMPL); \
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break;
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#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
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case OP: \
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panic("attempted to execute a linking opcode");
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#define CONNECT(OP)
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#define DECLARE_FAULT(FAULT) \
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{ /* uncaught... */break; }
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#include "machine.def"
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default:
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panic("attempted to execute a bogus opcode");
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}
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/* execute next instruction */
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regs.regs_PC = regs.regs_NPC;
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regs.regs_NPC += sizeof(md_inst_t);
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}
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#endif /* USE_JUMP_TABLE */
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}
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