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Merge pull request #1812 from freechipsproject/add_cover_points_pmp 

Adding cover points for pmp permission, and access
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Srivatsa Yogendra 2019-02-03 16:00:56 -08:00 committed by GitHub
parent f923a082b2 178a93b587
commit f52950325b
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1 changed files with 14 additions and 0 deletions
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14
src/main/scala/rocket/PMP.scala
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@ -7,6 +7,7 @@ import Chisel.ImplicitConversions._
import freechips.rocketchip.config._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
class PMPConfig extends Bundle {
val l = Bool()
@ -161,6 +162,19 @@ class PMPChecker(lgMaxSize: Int)(implicit p: Parameters) extends CoreModule()(p)
val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)
val ignore = default && !pmp.cfg.l
val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)
for ((name, idx) <- Seq("no", "TOR", "NA4", "NAPOT").zipWithIndex)
cover(!default && pmp.cfg.a === idx, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting")
cover(!default && pmp.cfg.l === 0x1, s"The cfg lock is set to high ", "Cover PMP lock mode setting")
// Not including Write and no Read permission as the combination is reserved
for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty)
cover(!default && (Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx), s"The permission is set to ${name} access ", "Cover PMP access permission setting")
for ((name, idx) <- Seq("", "TOR", "NA4", "NAPOT").zipWithIndex; if name.nonEmpty)
cover(!ignore && hit && aligned && pmp.cfg.a === idx, s"The access matches ${name} mode ", "Cover PMP access")
val cur = Wire(init = pmp)
cur.cfg.r := (aligned && pmp.cfg.r) || ignore
cur.cfg.w := (aligned && pmp.cfg.w) || ignore