Merge pull request #1854 from freechipsproject/mimpid-parameter
Make the mimpid CSR value a parameter
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commit
cf67a65d42
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@ -163,6 +163,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: Nil = Enum(UInt(), 8)
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val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: Nil = Enum(UInt(), 8)
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val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush
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val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush
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val flushed = Reg(init=Bool(true))
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val flushed = Reg(init=Bool(true))
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val flushing = Reg(init=Bool(false))
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val cached_grant_wait = Reg(init=Bool(false))
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val cached_grant_wait = Reg(init=Bool(false))
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val release_ack_wait = Reg(init=Bool(false))
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val release_ack_wait = Reg(init=Bool(false))
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val can_acquire_before_release = !release_ack_wait && release_queue_empty
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val can_acquire_before_release = !release_ack_wait && release_queue_empty
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@ -330,7 +331,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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dontTouch(s2_victim_dirty)
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dontTouch(s2_victim_dirty)
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val s2_update_meta = s2_hit_state =/= s2_new_hit_state
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val s2_update_meta = s2_hit_state =/= s2_new_hit_state
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val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready
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val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready
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val s2_dont_nack_flush = supports_flush && (s2_cmd_flush_all && flushed || s2_cmd_flush_line)
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val s2_dont_nack_flush = supports_flush && (s2_cmd_flush_all && flushed && !flushing || s2_cmd_flush_line)
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io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_flush && !s2_valid_hit
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io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_flush && !s2_valid_hit
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when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true }
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when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true }
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@ -788,7 +789,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val resetting = RegInit(false.B)
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val resetting = RegInit(false.B)
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if (!usingDataScratchpad)
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if (!usingDataScratchpad)
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when (RegNext(reset)) { resetting := true }
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when (RegNext(reset)) { resetting := true }
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val flushing = Reg(init=Bool(false))
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val flushCounter = Reg(init=UInt(nSets * (nWays-1), log2Ceil(nSets * nWays)))
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val flushCounter = Reg(init=UInt(nSets * (nWays-1), log2Ceil(nSets * nWays)))
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val flushCounterNext = flushCounter +& 1
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val flushCounterNext = flushCounter +& 1
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val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays
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val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays
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@ -806,8 +806,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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// Only flush D$ on FENCE.I if some cached executable regions are untracked.
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// Only flush D$ on FENCE.I if some cached executable regions are untracked.
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if (supports_flush) {
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if (supports_flush) {
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when (s2_valid_masked && s2_cmd_flush_all) {
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when (s2_valid_masked && s2_cmd_flush_all) {
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when (!flushed) {
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when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) {
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flushing := !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR
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flushing := true
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}
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}
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}
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}
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@ -38,6 +38,7 @@ case class RocketCoreParams(
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branchPredictionModeCSR: Boolean = false,
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branchPredictionModeCSR: Boolean = false,
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clockGate: Boolean = false,
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clockGate: Boolean = false,
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mvendorid: Int = 0, // 0 means non-commercial implementation
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mvendorid: Int = 0, // 0 means non-commercial implementation
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mimpid: Int = 0x20181004, // release date in BCD
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mulDiv: Option[MulDivParams] = Some(MulDivParams()),
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mulDiv: Option[MulDivParams] = Some(MulDivParams()),
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fpu: Option[FPUParams] = Some(FPUParams())
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fpu: Option[FPUParams] = Some(FPUParams())
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) extends CoreParams {
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) extends CoreParams {
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@ -83,8 +84,7 @@ class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocket
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def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid))
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def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid))
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// mimpid encodes a release version in the form of a BCD-encoded datestamp.
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// mimpid encodes a release version in the form of a BCD-encoded datestamp.
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// Past releases: <none>
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def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid))
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def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(0x20181004))
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override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
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override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
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}
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}
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