Merge pull request #1849 from freechipsproject/fpu-clock-gate
Move FPU load pipeline register into ungated clock domain
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commit
d29c1ac9b6
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@ -680,6 +680,12 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
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val ex_ra = List.fill(3)(Reg(UInt()))
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// load response
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val load_wb = Reg(next=io.dmem_resp_val)
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val load_wb_double = RegEnable(io.dmem_resp_type(0), io.dmem_resp_val)
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val load_wb_data = RegEnable(io.dmem_resp_data, io.dmem_resp_val)
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val load_wb_tag = RegEnable(io.dmem_resp_tag, io.dmem_resp_val)
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@chiselName class FPUImpl { // entering gated-clock domain
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val req_valid = ex_reg_valid || io.cp_req.valid
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@ -705,12 +711,6 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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val mem_ctrl = RegEnable(ex_ctrl, req_valid)
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val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
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// load response
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val load_wb = Reg(next=io.dmem_resp_val)
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val load_wb_double = RegEnable(io.dmem_resp_type(0), io.dmem_resp_val)
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val load_wb_data = RegEnable(io.dmem_resp_data, io.dmem_resp_val)
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val load_wb_tag = RegEnable(io.dmem_resp_tag, io.dmem_resp_val)
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// regfile
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val regfile = Mem(32, Bits(width = fLen+1))
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when (load_wb) {
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