HintHandler: rewrite for simpler hardware
This commit is contained in:
Wesley W. Terpstra
parent
d898b3662e
commit
79b392377d
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@ -2,88 +2,80 @@
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package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.Repeater
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import scala.math.min
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// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
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class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
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class TLHintHandler(passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
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{
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val node = TLAdapterNode(
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clientFn = { c => if (!supportClients) c else c.copy(minLatency = min(1, c.minLatency), clients = c.clients .map(_.copy(supportsHint = TransferSizes(1, c.maxTransfer)))) },
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managerFn = { m => if (!supportManagers) m else m.copy(minLatency = min(1, m.minLatency), managers = m.managers.map(_.copy(supportsHint = TransferSizes(1, m.maxTransfer)))) })
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clientFn = { cp =>
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cp.copy(clients = cp.clients.map { c => c.copy(
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sourceId = IdRange(c.sourceId.start*2, c.sourceId.end*2))})},
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managerFn = { mp =>
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mp.copy(managers = mp.managers.map { m => m.copy(
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supportsHint = if (m.supportsHint && passthrough) m.supportsHint else m.supportsPutPartial)})})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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// Don't add support for clients if there is no BCE channel
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val bce = edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
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require (!supportClients || bce)
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out <> in
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// Does it even make sense to add the HintHandler?
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val smartClients = edgeIn.client.clients.map(_.supportsHint.max == edgeIn.client.maxTransfer).reduce(_&&_)
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val smartManagers = edgeOut.manager.managers.map(_.supportsHint.max == edgeOut.manager.maxTransfer).reduce(_&&_)
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// Does the HintHandler help with this message?
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val help = in.a.bits.opcode === TLMessages.Hint && (!passthrough.B ||
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edgeOut.manager.fastProperty(in.a.bits.address, _.supportsHint.none, (b:Boolean) => b.B))
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val mapPP = WireInit(help)
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if (supportManagers && !(passthrough && smartManagers)) {
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val address = edgeIn.address(in.a.bits)
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val handleA = if (passthrough) !edgeOut.manager.supportsHintFast(address, edgeIn.size(in.a.bits)) else Bool(true)
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val hintBitsAtA = handleA && in.a.bits.opcode === TLMessages.Hint
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val hint = Wire(out.d)
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hint.valid := in.a.valid && hintBitsAtA
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out.a.valid := in.a.valid && !hintBitsAtA
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in.a.ready := Mux(hintBitsAtA, hint.ready, out.a.ready)
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hint.bits := edgeIn.HintAck(in.a.bits)
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out.a.bits := in.a.bits
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TLArbiter(TLArbiter.lowestIndexFirst)(in.d, (edgeOut.numBeats1(out.d.bits), out.d), (UInt(0), Queue(hint, 1)))
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} else {
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out.a.valid := in.a.valid
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in.a.ready := out.a.ready
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out.a.bits := in.a.bits
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in.d.valid := out.d.valid
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out.d.ready := in.d.ready
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in.d.bits := out.d.bits
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// To handle multi-beat Hints, we need to extend the Hint when creating a PutPartial
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// However, when used between a device (SRAM/RegisterRouter/etc) and a Fragmenter, this is not needed
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val needRepeater = (edgeIn.manager.managers zip edgeOut.manager.managers) exists { case (in, out) =>
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!(out.supportsHint && passthrough) && out.supportsPutPartial.max > edgeOut.manager.beatBytes
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}
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if (supportClients && !(passthrough && smartClients)) {
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val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source, edgeOut.size(out.b.bits)) else Bool(true)
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val hintBitsAtB = handleB && out.b.bits.opcode === TLMessages.Hint
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val hint = Wire(in.c)
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val a = if (!needRepeater) in.a else {
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val repeater = Module(new Repeater(in.a.bits))
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val mux = Wire(chiselTypeOf(in.a))
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hint.valid := out.b.valid && hintBitsAtB
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in.b.valid := out.b.valid && !hintBitsAtB
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out.b.ready := Mux(hintBitsAtB, hint.ready, in.b.ready)
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repeater.io.repeat := mapPP && !edgeIn.last(out.a)
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repeater.io.enq <> in.a
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// Work-around broken chisel3 <>
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out.a.bits := mux.bits
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out.a.valid := mux.valid
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mux.ready := out.a.ready
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hint.bits := edgeOut.HintAck(out.b.bits)
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in.b.bits := out.b.bits
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// Only some signals need to be repeated
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mux.bits.opcode := in.a.bits.opcode // ignored when full
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mux.bits.param := in.a.bits.param // ignored when full
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mux.bits.size := repeater.io.deq.bits.size
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mux.bits.source := repeater.io.deq.bits.source
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mux.bits.address := repeater.io.deq.bits.address
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mux.bits.data := in.a.bits.data // irrelevant when full (mask = 0)
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mux.bits.mask := in.a.bits.mask // ignored when full
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mux.bits.corrupt := in.a.bits.corrupt // irrelevant when full (mask = 0)
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TLArbiter(TLArbiter.lowestIndexFirst)(out.c, (edgeIn.numBeats1(in.c.bits), in.c), (UInt(0), Queue(hint, 1)))
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} else if (bce) {
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in.b.valid := out.b.valid
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out.b.ready := in.b.ready
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in.b.bits := out.b.bits
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mux.valid := repeater.io.deq.valid
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repeater.io.deq.ready := mux.ready
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out.c.valid := in.c.valid
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in.c.ready := out.c.ready
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out.c.bits := in.c.bits
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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mapPP := repeater.io.full || help
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mux
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}
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if (bce) {
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// Pass E through unchanged
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out.e.valid := in.e.valid
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in.e.ready := out.e.ready
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out.e.bits := in.e.bits
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} else {
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in.e.ready := Bool(true)
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out.e.valid := Bool(false)
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// Transform Hint to PutPartialData
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out.a.bits.opcode := Mux(mapPP, TLMessages.PutPartialData, a.bits.opcode)
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out.a.bits.param := Mux(mapPP, 0.U, a.bits.param)
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out.a.bits.mask := Mux(mapPP, 0.U, a.bits.mask)
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out.a.bits.source := a.bits.source << 1 | mapPP
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// Transform AccessAck to HintAck
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in.d.bits.source := out.d.bits.source >> 1
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in.d.bits.opcode := Mux(out.d.bits.source(0), TLMessages.HintAck, out.d.bits.opcode)
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if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
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in.b.bits.source := out.b.bits.source >> 1
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out.c.bits.source := in.c.bits.source << 1
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}
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}
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}
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@ -91,9 +83,9 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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object TLHintHandler
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{
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def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
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def apply(passthrough: Boolean = true)(implicit p: Parameters): TLNode =
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{
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val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
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val hints = LazyModule(new TLHintHandler(passthrough))
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hints.node
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}
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}
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@ -123,5 +115,5 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
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class TLRAMHintHandlerTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new TLRAMHintHandler(txns)).module)
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io.finished := dut.io.finished
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io <> dut.io
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}
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@ -46,6 +46,7 @@ class WithTLSimpleUnitTests extends Config((site, here, up) => {
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Module(new TLRAMSimpleTest(4, txns=15*txns, timeout=timeout)),
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Module(new TLRAMSimpleTest(16, txns=15*txns, timeout=timeout)),
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Module(new TLRAMZeroDelayTest(4, txns=15*txns, timeout=timeout)),
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Module(new TLRAMHintHandlerTest( txns=15*txns, timeout=timeout)),
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Module(new TLFuzzRAMTest( txns= 3*txns, timeout=timeout)),
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Module(new TLRR0Test( txns= 3*txns, timeout=timeout)),
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Module(new TLRR1Test( txns= 3*txns, timeout=timeout)),
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