tilelink: enhance trivial arbiters to reduce to nothing

src/main/scala/tilelink/Arbiter.scala

@@ -42,6 +42,8 @@ object TLArbiter
   def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*) {
     if (sources.isEmpty) {
       sink.valid := Bool(false)
+    } else if (sources.size == 1) {
+      sink <> sources.head._2
     } else {
       val pairs = sources.toList
       val beatsIn = pairs.map(_._1)
@@ -77,15 +79,10 @@ object TLArbiter
       val muxState = Mux(idle, winner, state)
       state := muxState
 
-      if (sources.size > 1) {
-        val allowed = Mux(idle, readys, state)
-        (sourcesIn zip allowed) foreach { case (s, r) =>
-          s.ready := sink.ready && r
-        }
-      } else {
-        sourcesIn(0).ready := sink.ready
+      val allowed = Mux(idle, readys, state)
+      (sourcesIn zip allowed) foreach { case (s, r) =>
+        s.ready := sink.ready && r
       }
-
       sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
       sink.bits := Mux1H(muxState, sourcesIn.map(_.bits))
     }

src/main/scala/tilelink/Xbar.scala

@@ -242,7 +242,7 @@ object TLXbar
     val filtered = Wire(Vec(select.size, input))
     for (i <- 0 until select.size) {
       filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
-      filtered(i).valid := input.valid && select(i)
+      filtered(i).valid := input.valid && (select(i) || Bool(select.size == 1))
     }
     input.ready := Mux1H(select, filtered.map(_.ready))
     filtered