This reverts commit c69607cfd5
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parent
dd89f987cb
commit
6eac64c73a
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@ -89,23 +89,6 @@ class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocket
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override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
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}
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// this bundle is used to expose some internal core signals
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// to verification monitors which sample instruction commits
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class CoreMonitorBundle(val xLen: Int) extends Bundle {
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val hartid = UInt(width = xLen)
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val timer = UInt(width = 32)
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val valid = Bool()
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val pc = UInt(width = xLen)
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val wrdst = UInt(width = 5)
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val wrdata = UInt(width = xLen)
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val wren = Bool()
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val rd0src = UInt(width = 5)
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val rd0val = UInt(width = xLen)
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val rd1src = UInt(width = 5)
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val rd1val = UInt(width = xLen)
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val inst = UInt(width = 32)
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}
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@chiselName
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class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
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with HasRocketCoreParameters
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@ -819,10 +802,24 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
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val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid))
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csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
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val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen))
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class CoreMonitorBundle extends Bundle {
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val hartid = UInt(width = hartIdLen)
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val time = UInt(width = 32)
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val valid = Bool()
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val pc = UInt(width = vaddrBitsExtended)
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val wrdst = UInt(width = 5)
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val wrdata = UInt(width = xLen)
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val wren = Bool()
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val rd0src = UInt(width = 5)
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val rd0val = UInt(width = xLen)
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val rd1src = UInt(width = 5)
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val rd1val = UInt(width = xLen)
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val inst = UInt(width = 32)
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}
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val coreMonitorBundle = Wire(new CoreMonitorBundle)
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coreMonitorBundle.hartid := io.hartid
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coreMonitorBundle.timer := csr.io.time(31,0)
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coreMonitorBundle.time := csr.io.time(31,0)
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coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception
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coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0)
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coreMonitorBundle.wrdst := Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0))
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@ -834,6 +831,8 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
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coreMonitorBundle.rd1val := Reg(next=Reg(next=ex_rs(1)))
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coreMonitorBundle.inst := csr.io.trace(0).insn
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p(BundleMonitorKey).foreach { _ ("rocket_core_monitor", coreMonitorBundle) }
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if (enableCommitLog) {
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val t = csr.io.trace(0)
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val rd = wb_waddr
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@ -862,7 +861,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
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}
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else {
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printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
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coreMonitorBundle.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,
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coreMonitorBundle.hartid, coreMonitorBundle.time, coreMonitorBundle.valid,
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coreMonitorBundle.pc,
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coreMonitorBundle.wrdst, coreMonitorBundle.wrdata, coreMonitorBundle.wren,
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coreMonitorBundle.rd0src, coreMonitorBundle.rd0val,
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@ -0,0 +1,12 @@
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// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import freechips.rocketchip.config._
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import Chisel._
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// This key allows to pass a bundle monitor object through parameters
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// It does not define acutal implementation
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case object BundleMonitorKey extends Field[Option[(String, Bundle) => Unit]] (None)
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