Merge pull request #1730 from freechipsproject/misc-fixes
Fix a few issues with multi-chip designs
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0c2664cebe
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@ -60,11 +60,12 @@ class AXI4ToTL(wcorrupt: Boolean = false)(implicit p: Parameters) extends LazyMo
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// Look for an Error device to redirect bad requests
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val errorDevs = edgeOut.manager.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
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require (!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
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val error = errorDevs.head.address.head.base
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require (errorDevs.head.supportsPutPartial.contains(edgeOut.manager.maxTransfer),
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s"Error device supports ${errorDevs.head.supportsPutPartial} PutPartial but must support ${edgeOut.manager.maxTransfer}")
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require (errorDevs.head.supportsGet.contains(edgeOut.manager.maxTransfer),
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s"Error device supports ${errorDevs.head.supportsGet} Get but must support ${edgeOut.manager.maxTransfer}")
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val errorDev = errorDevs.maxBy(_.maxTransfer)
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val error = errorDev.address.head.base
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require (errorDev.supportsPutPartial.contains(edgeOut.manager.maxTransfer),
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s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support ${edgeOut.manager.maxTransfer}")
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require (errorDev.supportsGet.contains(edgeOut.manager.maxTransfer),
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s"Error device supports ${errorDev.supportsGet} Get but must support ${edgeOut.manager.maxTransfer}")
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val r_out = Wire(out.a)
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val r_size1 = in.ar.bits.bytes1()
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@ -185,13 +185,13 @@ abstract class BaseTile(tileParams: TileParams, val crossing: ClockCrossingType)
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}
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protected def makeSlaveBoundaryBuffers(implicit p: Parameters) = TLBuffer(BufferParams.none)
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def crossSlavePort(): TLInwardNode = { DisableMonitors { implicit p =>
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def crossSlavePort(): TLInwardNode = { DisableMonitors { implicit p => FlipRendering { implicit p =>
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val tlSlaveXing = this.crossIn(crossing match {
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case RationalCrossing(_) => slaveNode :*= this { makeSlaveBoundaryBuffers }
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case _ => slaveNode
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})
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tlSlaveXing(crossing)
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} }
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} } }
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def crossIntIn(): IntInwardNode = crossIntIn(intInwardNode)
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def crossIntOut(): IntOutwardNode = crossIntOut(intOutwardNode)
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@ -120,11 +120,12 @@ class AddressAdjuster(mask: BigInt)(implicit p: Parameters) extends LazyModule {
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val (parent, parentEdge) = node.in(0)
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val (remote, remoteEdge) = node.out(0)
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val (local, localEdge) = node.out(1)
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require (localEdge.manager.beatBytes == remoteEdge.manager.beatBytes)
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require (localEdge.manager.beatBytes == remoteEdge.manager.beatBytes,
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s"Port width mismatch ${localEdge.manager.beatBytes} (${localEdge.manager.managers.map(_.name)}) != ${remoteEdge.manager.beatBytes} (${remoteEdge.manager.managers.map(_.name)})")
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// Which address within the mask routes to local devices?
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val local_address = (bits zip chip_id.bundle.toBools).foldLeft(0.U) {
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case (acc, (bit, sel)) => acc | Mux(sel, 0.U, bit.U)
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case (acc, (bit, sel)) => acc | Mux(sel, bit.U, 0.U)
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}
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// Route A by address, but reroute unsupported operations
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@ -160,9 +161,15 @@ class AddressAdjuster(mask: BigInt)(implicit p: Parameters) extends LazyModule {
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// Rewrite sink in D
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val sink_threshold = localEdge.manager.endSinkId.U // more likely to be 0 than remote.endSinkId
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val local_d = WireInit(chiselTypeOf(parent.d), local.d) // type-cast, because 'sink' width differs
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val remote_d = WireInit(chiselTypeOf(parent.d), remote.d)
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remote_d.bits.sink := remote.d.bits.sink + sink_threshold
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val local_d = Wire(chiselTypeOf(parent.d)) // type-cast, because 'sink' width differs
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local.d.ready := local_d.ready
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local_d.valid := local.d.valid
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local_d.bits := local.d.bits
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val remote_d = Wire(chiselTypeOf(parent.d))
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remote.d.ready := remote_d.ready
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remote_d.valid := remote.d.valid
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remote_d.bits := remote.d.bits
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remote_d.bits.sink := remote.d.bits.sink +& sink_threshold
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TLArbiter.robin(parentEdge, parent.d, local_d, remote_d)
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if (parentEdge.manager.anySupportAcquireB && parentEdge.client.anySupportProbe) {
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@ -186,6 +193,7 @@ class AddressAdjuster(mask: BigInt)(implicit p: Parameters) extends LazyModule {
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remote.e.valid := parent.e.valid && !e_local
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local .e.bits := parent.e.bits
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remote.e.bits := parent.e.bits
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remote.e.bits.sink := parent.e.bits.sink - sink_threshold
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}
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}
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}
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