From b50b1959b5b19aa4405fcddbc7c42cb3b2f80470 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Nov 2018 18:48:16 -0800 Subject: [PATCH 1/4] AXI4ToTL: always select the error device with the largest transfer --- src/main/scala/amba/axi4/ToTL.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/main/scala/amba/axi4/ToTL.scala b/src/main/scala/amba/axi4/ToTL.scala index ab40175f..f5573f6b 100644 --- a/src/main/scala/amba/axi4/ToTL.scala +++ b/src/main/scala/amba/axi4/ToTL.scala @@ -60,11 +60,12 @@ class AXI4ToTL(wcorrupt: Boolean = false)(implicit p: Parameters) extends LazyMo // Look for an Error device to redirect bad requests val errorDevs = edgeOut.manager.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require (!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") - val error = errorDevs.head.address.head.base - require (errorDevs.head.supportsPutPartial.contains(edgeOut.manager.maxTransfer), - s"Error device supports ${errorDevs.head.supportsPutPartial} PutPartial but must support ${edgeOut.manager.maxTransfer}") - require (errorDevs.head.supportsGet.contains(edgeOut.manager.maxTransfer), - s"Error device supports ${errorDevs.head.supportsGet} Get but must support ${edgeOut.manager.maxTransfer}") + val errorDev = errorDevs.maxBy(_.maxTransfer) + val error = errorDev.address.head.base + require (errorDev.supportsPutPartial.contains(edgeOut.manager.maxTransfer), + s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support ${edgeOut.manager.maxTransfer}") + require (errorDev.supportsGet.contains(edgeOut.manager.maxTransfer), + s"Error device supports ${errorDev.supportsGet} Get but must support ${edgeOut.manager.maxTransfer}") val r_out = Wire(out.a) val r_size1 = in.ar.bits.bytes1() From 16a94678aabbb7b5c13895820974e17bef448465 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Nov 2018 19:41:14 -0800 Subject: [PATCH 2/4] AddressAdjuster: report which slaves have conflicting width --- src/main/scala/tilelink/AddressAdjuster.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/AddressAdjuster.scala b/src/main/scala/tilelink/AddressAdjuster.scala index da8554a3..9f279ae3 100644 --- a/src/main/scala/tilelink/AddressAdjuster.scala +++ b/src/main/scala/tilelink/AddressAdjuster.scala @@ -120,7 +120,8 @@ class AddressAdjuster(mask: BigInt)(implicit p: Parameters) extends LazyModule { val (parent, parentEdge) = node.in(0) val (remote, remoteEdge) = node.out(0) val (local, localEdge) = node.out(1) - require (localEdge.manager.beatBytes == remoteEdge.manager.beatBytes) + require (localEdge.manager.beatBytes == remoteEdge.manager.beatBytes, + s"Port width mismatch ${localEdge.manager.beatBytes} (${localEdge.manager.managers.map(_.name)}) != ${remoteEdge.manager.beatBytes} (${remoteEdge.manager.managers.map(_.name)})") // Which address within the mask routes to local devices? val local_address = (bits zip chip_id.bundle.toBools).foldLeft(0.U) { From 2303e93e57b018c460a4a59219e2799239f127eb Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Nov 2018 19:42:08 -0800 Subject: [PATCH 3/4] Tiles: place at the top of the chip graph --- src/main/scala/tile/BaseTile.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index d27e251a..752289bd 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -182,13 +182,13 @@ abstract class BaseTile(tileParams: TileParams, val crossing: ClockCrossingType) } protected def makeSlaveBoundaryBuffers(implicit p: Parameters) = TLBuffer(BufferParams.none) - def crossSlavePort(): TLInwardNode = { DisableMonitors { implicit p => + def crossSlavePort(): TLInwardNode = { DisableMonitors { implicit p => FlipRendering { implicit p => val tlSlaveXing = this.crossIn(crossing match { case RationalCrossing(_) => slaveNode :*= this { makeSlaveBoundaryBuffers } case _ => slaveNode }) tlSlaveXing(crossing) - } } + } } } def crossIntIn(): IntInwardNode = crossIntIn(intInwardNode) def crossIntOut(): IntOutwardNode = crossIntOut(intOutwardNode) From 6ba11a3159157b3664c742dcc390f3106c2fdb53 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 30 Nov 2018 19:07:33 -0800 Subject: [PATCH 4/4] AddressAdjuster: fix untested and broken code --- src/main/scala/tilelink/AddressAdjuster.scala | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/main/scala/tilelink/AddressAdjuster.scala b/src/main/scala/tilelink/AddressAdjuster.scala index 9f279ae3..314b3986 100644 --- a/src/main/scala/tilelink/AddressAdjuster.scala +++ b/src/main/scala/tilelink/AddressAdjuster.scala @@ -125,7 +125,7 @@ class AddressAdjuster(mask: BigInt)(implicit p: Parameters) extends LazyModule { // Which address within the mask routes to local devices? val local_address = (bits zip chip_id.bundle.toBools).foldLeft(0.U) { - case (acc, (bit, sel)) => acc | Mux(sel, 0.U, bit.U) + case (acc, (bit, sel)) => acc | Mux(sel, bit.U, 0.U) } // Route A by address, but reroute unsupported operations @@ -161,9 +161,15 @@ class AddressAdjuster(mask: BigInt)(implicit p: Parameters) extends LazyModule { // Rewrite sink in D val sink_threshold = localEdge.manager.endSinkId.U // more likely to be 0 than remote.endSinkId - val local_d = WireInit(chiselTypeOf(parent.d), local.d) // type-cast, because 'sink' width differs - val remote_d = WireInit(chiselTypeOf(parent.d), remote.d) - remote_d.bits.sink := remote.d.bits.sink + sink_threshold + val local_d = Wire(chiselTypeOf(parent.d)) // type-cast, because 'sink' width differs + local.d.ready := local_d.ready + local_d.valid := local.d.valid + local_d.bits := local.d.bits + val remote_d = Wire(chiselTypeOf(parent.d)) + remote.d.ready := remote_d.ready + remote_d.valid := remote.d.valid + remote_d.bits := remote.d.bits + remote_d.bits.sink := remote.d.bits.sink +& sink_threshold TLArbiter.robin(parentEdge, parent.d, local_d, remote_d) if (parentEdge.manager.anySupportAcquireB && parentEdge.client.anySupportProbe) { @@ -187,6 +193,7 @@ class AddressAdjuster(mask: BigInt)(implicit p: Parameters) extends LazyModule { remote.e.valid := parent.e.valid && !e_local local .e.bits := parent.e.bits remote.e.bits := parent.e.bits + remote.e.bits.sink := parent.e.bits.sink - sink_threshold } } }