64 lines
3.0 KiB
Markdown
64 lines
3.0 KiB
Markdown
# Centrifuge - A Unified Approach to Generate RISC-V Accelerator SoC
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## 1. Centrifuge Setup
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1) Set up the Chipyard repo following the instruction [here](https://chipyard.readthedocs.io/en/latest/Chipyard-Basics/Initial-Repo-Setup.html#initial-repository-setup). For more Chipyard related info, visit the Chipyard page (https://chipyard.readthedocs.io/en/latest/). Please check out Chipyard version 1.8.1.
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2) (OPTIONAL for FPGA-accelerated simulation) Set up the FireSim repo.
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For more FireSim related info, please refer to FireSim’s documentation (https://docs.fires.im/en/latest/index.html).
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For using FireSim in Chipyard, refer to (https://chipyard.readthedocs.io/en/latest/Simulation/FPGA-Accelerated-Simulation.html).
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3) Clone Centrifuge and set up its dependencies.
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Git clone the current repo to the Chipard tools directory.
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```
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pushd chipyard/tools && git clone -b python-dev-new git@github.com:hqjenny/centrifuge.git && popd
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```
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Set up riscv-pk for accelerator calls and applies patches to existing tools.
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```
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cd tools/centrifuge && source scripts/hls-setup-a-machine.sh && cd ../..
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pushd tools/centrifuge && pip3 install -r python-requirements.txt && popd
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```
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## 2. Running Centrifuge
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1) Before running Centrifuge, source the env setup scripts.
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It sets an environmental variable `RDIR` to the root directory of the Chipyard, which we used to construct paths in the scritps.
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```
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source tools/centrifuge/env.sh
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```
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### 2.1 Vector Add Example
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Run Centrifuge to generate the accelerator SoC defined in `vadd_soc.json`.
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```
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cd $RDIR/tools/centrifuge/deploy
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./centrifuge generate_hw -c ../examples/vadd_proj/vadd_soc.json
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./centrifuge generate_sw -c ../examples/vadd_proj/vadd_soc.json
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```
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This also generates the sw helper functions to invoke the accelerator. The generated sw wrapper `accel_wrapper.c` and `accel_wrapper.h`is under the hardware path `$RDIR/tools/centrifuge/examples/vadd_proj/centrifuge_wrappers/`.
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4) Software Compilation
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Run the following command to invoke compilation for bare-metal.
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```
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./centrifuge generate_sw -c ../examples/vadd_proj/vadd_soc.json
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```
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We currently have the vadd RoCC example code and Makefile under example directory and are working on migrating the compilation flow from perl to python.
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```
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cd $RDIR/tools/centrifuge/examples/vadd && make
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```
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The generated `vadd.bm.rv` is a software only reference code for vadd and `vadd.bm_accel.rv` is the baremetal code for calling the RoCC vadd accelerator
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5) Run VCS/Verilator Simulation
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To run VCS simulation,
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```
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./centrifuge run_vcs -c ../examples/vadd_proj/vadd_soc.json
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```
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Replace `run_vcs` with `run_verilator` for Verilator runs.
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This command generates a simulation executable called `simv-example-HLSRocketConfig-debug` under `$RDIR/sims/vcs/`.
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This executable is a simulator that has been compiled based on the design that was built.
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You can then use this executable to run any compatible RV64 code.
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For instance, to invoke the accelerator in bare-metal software, run:
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```
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cd $RDIR/sims/vcs/
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./simv-example-HLSRocketConfig-debug <sw binary>
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```
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