Fix hw generation bugs including not allowing understore in Config name; Fail to add Parameteres for HLS configs

deploy/centrifuge.py

@@ -21,7 +21,7 @@ from os.path import dirname as up
 
 def construct_centrifuge_argparser():
     # parse command line args
-    parser = argparse.ArgumentParser(description='Centrifuge Script')
+    parser = argparse.ArgumentParser(description='Centrifuge Script', formatter_class=argparse.RawTextHelpFormatter)
     parser.add_argument('task', 
                         type=str,
                         help="""Management task to run. 

deploy/pkg/buildaccel/generate_build_sbt.py

@@ -37,8 +37,9 @@ lazy val ${ACCEL} = (project in file("${DIR}"))
     accel_config_str += accel_template.substitute(d) 
 
     template_path = util.getOpt('template-dir') / 'build_sbt_template'
+    hls_soc_name_str = accel_conf.accel_name + ',' 
     config_dict = {
-        'HLS_SOC_NAME': accel_conf.accel_name,  
+        'HLS_SOC_NAME': hls_soc_name_str,  
         'HLS_SOC_CONFIG': accel_config_str
     }
     chipyard_dir = util.getOpt('chipyard-dir')

deploy/pkg/buildaccel/generate_chisel.py

@@ -654,8 +654,10 @@ def generate_tl_module_stmt(inputs, outputs, buses):
                     "out_{0}.{1}.bits.last := " + out_str)
             elif matchWID: 
                 # TODO check if this is needed
-                assign_str = generate_AXI_signal(matchWID, 
-                    "out_{0}.{1}.bits.id := " + out_str)
+                #assign_str = generate_AXI_signal(matchWID, 
+                #    "out_{0}.{1}.bits.id := " + out_str)
+                # No such signal in TLtoAXI4
+                assign_str = ""
             elif matchWUSER: 
                 assign_str = ""
             elif matchAWWARREADY: 

deploy/pkg/buildaccel/generate_config.py

@@ -18,7 +18,7 @@ def generate_config(accel_conf):
     for accel in accel_conf.rocc_accels:
         import_str += "import hls_{0}.HLS{0}Control\n".format(accel.name)
     for accel in accel_conf.tl_accels:
-        import_str += "import hls_{0}._\n".format(accel.name)
+        import_str += "// import hls_{0}.WithHLS{0}\n".format(accel.name)
 
     rocc_arr = []
     rocc_template = Template("""(p: Parameters) => {
@@ -27,7 +27,7 @@ def generate_config(accel_conf):
         }""")
 
     for idx, accel in enumerate(accel_conf.rocc_accels):
-        d = {'ACCEL': 'hls_' + accel.name, 'IDX': idx}
+        d = {'ACCEL': accel.name, 'IDX': idx}
         rocc_arr.append(rocc_template.substitute(d)) 
     rocc_str = ",\n        ".join(rocc_arr)
 
@@ -35,27 +35,54 @@ def generate_config(accel_conf):
         rocc_str += "," 
 
     tl_peri_str = "" 
-    tl_peri_imp_str = ""
+    tl_trait_str = ""
+    tl_trait_imp_str = ""
     for accel in accel_conf.tl_accels:
-        tl_peri_str += "\n    with HasPeripheryHLS{}AXI".format(accel.name)
-        tl_peri_imp_str += "\n    with HasPeripheryHLS{}AXIImp".format(accel.name)
+        tl_peri_str += "    new WithHLS{} ++\n".format(accel.name)
+        tl_trait_str += "  with hls_{0}.CanHavePeripheryHLS{0}AXI\n".format(accel.name)
+        tl_trait_imp_str += "  with hls_{0}.CanHavePeripheryHLS{0}AXIImp\n".format(accel.name)
+
 
     template_dir = util.getOpt('template-dir')
     config_dict = {
-        'SOC_NAME': accel_conf.accel_name,
+        #'SOC_NAME': accel_conf.accel_name,
         'HLS_SOC_IMPORT': import_str,  
         'ROCC_CONFIG': rocc_str,
         'TL_PERIPHERY': tl_peri_str,
-        'TL_PERIPHERY_IMP': tl_peri_imp_str,
+        #'TL_PERIPHERY_IMP': tl_peri_imp_str,
     }
     
     template_path = template_dir / 'HLSConfig_scala_template'
-    output_path =  accel_conf.hw_scala_dir / 'HLSConfig.scala'
+    output_path =  accel_conf.chipyard_scala_dir / 'config' / 'HLSConfig.scala'
     util.generate_file(template_path, config_dict, output_path)
     logger.info("\t\tGenerate HLSConfig.scala: {}".format(output_path))
 
-    template_path = template_dir / 'HLSFireSimConfig_scala_template'
-    output_path =  accel_conf.hw_scala_dir / 'HLSFireSimConfig.scala'
-    util.generate_file(template_path, config_dict, output_path)
-    logger.info("\t\tGenerate HLSFireSimConfig.scala: {}".format(output_path))
+    config_dict = {
+        'SOC_NAME': accel_conf.accel_name,
+        'TL_TRAIT': tl_trait_str,
+        'TL_TRAIT_IMP': tl_trait_imp_str,
+    }
+
+    template_path = template_dir / 'Top_scala_template'
+    output_path =  accel_conf.chipyard_scala_dir / 'Top.scala'
+    util.generate_file(template_path, config_dict, output_path)
+    logger.info("\t\tGenerate Top.scala: {}".format(output_path))
+
+
+    firesim_str ="""package firesim.firesim
+
+import java.io.File
+
+import chisel3._
+import chisel3.util.{log2Up}
+import freechips.rocketchip.config.{Parameters, Config}
+class HLSFireSimRocketChipConfig extends Config(
+    new WithDefaultFireSimBridges ++
+    new WithDefaultMemModel ++
+    new WithFireSimConfigTweaks ++
+    new chipyard.HLSRocketConfig)
+"""
+    output_path = accel_conf.firechip_scala_dir / 'HLSTargetConfig.scala'
+    with open(output_path, 'w') as f:
+        f.write(firesim_str)
 

deploy/pkg/buildaccel/generate_hw.py

@@ -40,7 +40,6 @@ def init_accel(accel_conf):
         logger.info("\tInitialize {}:".format(accel.prefix_id))
         init_proj_dir(accel)
         cp_src(accel)
-    util.mkdir_p(accel_conf.hw_scala_dir)
 
 def rm_accel(accel_conf):
     """Remove directories for the accel SoC"""

deploy/pkg/buildaccel/run_hls.py

@@ -18,13 +18,14 @@ logger.setLevel(logging.NOTSET)
 
 
 def modify_verilog(accel):
-    """ Update Verilog to make it compatible with our infrastructure
+    """ Update Verilog to make it compatible with chipyard simulators
         1. Add abs path to readmemh 
         2. Replace undefined 'bx signals to 1'b0
     """
     verilog_dir = accel.verilog_dir
     # list all verilog file
     verilog_files = list(verilog_dir.glob('**/*.v'))
+    logger.info("\t\tUpdate Verilog Files in {}".format(verilog_dir))
     for verilog_file in verilog_files:
         util.replace_str(verilog_file, '$readmemh("', "$readmemh(\"{}/".format(str(verilog_dir)))
         util.replace_str(verilog_file, "'bx", "1'b0")

deploy/pkg/util/accelconfig.py

@@ -20,6 +20,7 @@ class Accel(object):
 
         src_main_path = self.dir / 'src' / 'main'
         self.c_dir = src_main_path / 'c'
+        #self.verilog_dir = src_main_path / 'resources' / 'vsrc' 
         self.verilog_dir = src_main_path / 'verilog' 
         self.scala_dir = src_main_path / 'scala' 
 
@@ -58,11 +59,13 @@ class AccelConfig:
         self.chipyard_dir = chipyard_dir
         self.centrifuge_dir = centrifuge_dir
 
+        self.chipyard_scala_dir = self.chipyard_dir / 'generators' / 'chipyard' / 'src' / 'main' / 'scala' 
+        self.firechip_scala_dir = self.chipyard_dir / 'generators' / 'firechip' / 'src' / 'main' / 'scala'
         self.accel_name = self.accel_json_path.stem
         self.accel_json_dir = accel_json_path.parent
         self.gensw_dir = self.accel_json_dir / 'centrifuge_wrappers'
         self.hw_accel_dir = genhw_dir / self.accel_name
-        self.hw_scala_dir = self.hw_accel_dir / 'src' / 'main' / 'scala' 
+        self.hw_accel_scala_dir = self.hw_accel_dir / 'src' / 'main' / 'scala' 
         self.accel_json = self.parse_json(self.accel_json_path)
         self.rocc_accels = []
         self.tl_accels = []

deploy/support/templates/HLSConfig_scala_template

@@ -1,21 +1,20 @@
-package example
+package chipyard
 import chisel3._
 import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.config.{Parameters, Config}
 import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system._
 import freechips.rocketchip.system.DefaultConfig
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tilelink._     
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip._
 import testchipip._
-import sifive.blocks.devices.uart.{PeripheryUARTKey,UARTParams}
 
 import sifive.blocks.devices.uart._
 import java.io.File
-import ConfigValName._
 
 ${HLS_SOC_IMPORT}
 
@@ -29,23 +28,28 @@ class WithHLSRoCCExample extends Config((site, here, up) => {
     )
 })
 
-class ${SOC_NAME}HLSRocketConfig extends Config(
-    new WithHLSTop ++
-    new WithBootROM ++
-    new freechips.rocketchip.subsystem.WithInclusiveCache ++
+class HLSRocketConfig extends Config(
+    // IOBinders specify how to connect to IOs in our TestHarness
+    // These config fragments do not affect
+    new chipyard.iobinders.WithUARTAdapter ++       // Connect a SimUART adapter to display UART on stdout
+    new chipyard.iobinders.WithBlackBoxSimMem ++    // Connect simulated external memory
+    new chipyard.iobinders.WithTieOffInterrupts ++  // Do not simulate external interrupts
+    new chipyard.iobinders.WithTiedOffDebug ++      // Disconnect the debug module, since we use TSI for bring-up
+    new chipyard.iobinders.WithSimSerial ++         // Connect external SimSerial widget to drive TSI
+  
+    // Config fragments below this line affect hardware generation
+    // of the Top
+    new testchipip.WithTSI ++                  // Add a TSI (Test Serial Interface)  widget to bring-up the core
+    new chipyard.config.WithNoGPIO ++          // Disable GPIOs.
+    new chipyard.config.WithBootROM ++         // Use the Chipyard BootROM
+    new chipyard.config.WithRenumberHarts ++   // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op
+    new chipyard.config.WithUART ++            // Add a UART
+    new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
+    // ${TL_PERIPHERY} // Disable due to Error scala.Some cannot be cast to scala.Function1, and our accelerators currently do not have parameters  
     new WithHLSRoCCExample ++ 
-    new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+    new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+    new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+    new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+    new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+    new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
     new freechips.rocketchip.system.BaseConfig)
-
-class ${SOC_NAME}WithHLSTop extends Config((site, here, up) => {
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
-      Module(LazyModule(new ${SOC_NAME}TopWithHLS()(p)).module)
-})
-
-class ${SOC_NAME}TopWithHLS(implicit p: Parameters) extends Top ${TL_PERIPHERY}
-{
-    override lazy val module = new ${SOC_NAME}TopWithHLSModule(this)
-}
-
-class ${SOC_NAME}TopWithHLSModule(l: ${SOC_NAME}TopWithHLS) extends TopModule(l) ${TL_PERIPHERY_IMP}
-

deploy/support/templates/HLSFireSimConfig_scala_template

@@ -1,78 +0,0 @@
-package firesim.firesim
-
-import chisel3._
-import freechips.rocketchip._
-import freechips.rocketchip.tile._
-import freechips.rocketchip.rocket._
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters, Config}
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.util.{HeterogeneousBag}
-import freechips.rocketchip.amba.axi4.AXI4Bundle
-import freechips.rocketchip.config.{Field, Parameters}
-import freechips.rocketchip.diplomacy.LazyModule
-import utilities.{Subsystem, SubsystemModuleImp}
-import icenet._
-import firesim.util.DefaultFireSimHarness
-import testchipip._
-import testchipip.SerialAdapter.SERIAL_IF_WIDTH
-import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp}
-import sifive.blocks.devices.uart._
-import java.io.File
-
-import firesim.bridges._
-import firesim.util.{WithNumNodes}
-import firesim.configs._
-
-import FireSimValName._
-
-${HLS_SOC_IMPORT}
-
-class WithHLSRoCCExample extends Config((site, here, up) => {
-    case BuildRoCC => Seq(
-        ${ROCC_CONFIG}
-        (p: Parameters) => {
-            val translator = LazyModule(new TranslatorExample(OpcodeSet.custom3)(p))
-            translator 
-        }
-    )
-})
-
-class ${SOC_NAME}HLSFireSimRocketChipConfig extends Config(
-    new WithBootROM ++
-    new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
-    new WithExtMemSize(0x400000000L) ++ // 16GB
-    new WithoutTLMonitors ++
-    new WithUARTKey ++
-    new WithNICKey ++
-    new WithBlockDevice ++
-    new WithRocketL2TLBs(1024) ++
-    new WithPerfCounters ++
-    new WithInclusiveCache ++
-    new WithoutClockGating ++
-    new WithDefaultMemModel ++
-    new WithDefaultFireSimBridges ++
-    new WithHLSRoCCExample ++
-    new freechips.rocketchip.system.DefaultConfig)
-
-class ${SOC_NAME}FireSimTopWithHLSDUT(implicit p: Parameters) extends FireSimDUT ${TL_PERIPHERY}
-{
-    override lazy val module = new ${SOC_NAME}FireSimTopWithHLSModuleImp(this)
-}
-
-class ${SOC_NAME}FireSimTopWithHLSModuleImp[+L <: ${SOC_NAME}FireSimTopWithHLSDUT](l: L) extends FireSimModuleImp(l) ${TL_PERIPHERY_IMP}
-
-class ${SOC_NAME}FireSimTopWithHLS (implicit p: Parameters) extends DefaultFireSimHarness(() => new ${SOC_NAME}FireSimTopWithHLSDUT)
-
-class ${SOC_NAME}FireSimTopWithHLSNoNICDUT(implicit p: Parameters) extends FireSimNoNICDUT ${TL_PERIPHERY}
-{
-    override lazy val module = new ${SOC_NAME}FireSimTopWithHLSNoNICModuleImp(this)
-}
-
-class ${SOC_NAME}FireSimTopWithHLSNoNICModuleImp[+L <: ${SOC_NAME}FireSimTopWithHLSNoNICDUT](l: L) extends FireSimNoNICModuleImp(l) ${TL_PERIPHERY_IMP}
-
-class ${SOC_NAME}FireSimTopWithHLSNoNIC (implicit p: Parameters) extends DefaultFireSimHarness(() => new ${SOC_NAME}FireSimTopWithHLSNoNICDUT)

deploy/support/templates/Top_scala_template

@@ -7,7 +7,6 @@ import freechips.rocketchip.system._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 
-${HLS_SOC_IMPORT}
 // ------------------------------------
 // BOOM and/or Rocket Top Level Systems
 // ------------------------------------
@@ -23,8 +22,7 @@ class Top(implicit p: Parameters) extends System
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
   with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
-${TL_TRAIT}
-{
+${TL_TRAIT}{
   override lazy val module = new TopModule(this)
 }
 
@@ -37,4 +35,5 @@ class TopModule[+L <: Top](l: L) extends SystemModule(l)
   with icenet.CanHavePeripheryIceNICModuleImp
   with chipyard.example.CanHavePeripheryGCDModuleImp
   with freechips.rocketchip.util.DontTouch
+${TL_TRAIT_IMP}
 // DOC include end: Top

deploy/support/templates/chisel_rocc_accel_scala_template

@@ -1,6 +1,6 @@
 package hls_${FUNC}
 import Chisel._
-import chisel3.experimental.dontTouch
+import chisel3.dontTouch
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.config._
@@ -89,7 +89,7 @@ val rspBufferLen = 4
 val maxReqBytes = xLen/8
 val roccAddrWidth = coreMaxAddrBits
 val roccDataWidth = coreDataBits
-val roccTagWidth = coreDCacheReqTagBits
+val roccTagWidth = coreParams.dcacheReqTagBits
 val roccCmdWidth = M_SZ
 val roccTypWidth = log2Ceil(coreDataBytes.log2 + 1) 
 //val numTags = p(RoccMaxTaggedMemXacts)

deploy/support/templates/chisel_rocc_blackbox_scala_template

@@ -1,6 +1,6 @@
 package hls_${FUNC}
 import Chisel._
-import chisel3.experimental.dontTouch
+import chisel3.dontTouch
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util._

deploy/support/templates/chisel_tl_accel_scala_template

@@ -3,13 +3,16 @@ package hls_${FUNC}
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.util._ 
 import freechips.rocketchip.subsystem._
 
+//case class ${FUNC}Config()
+//case object ${FUNC}Key extends Field[Option[${FUNC}Config]](None)
+
 class HLS${FUNC}AXI (address: BigInt = 0x20000, beatBytes: Int = 8) (implicit p: Parameters) extends LazyModule {  
 
     val numInFlight = 8
@@ -55,11 +58,16 @@ class HLS${FUNC}AXIModule(outer: HLS${FUNC}AXI) extends LazyModuleImp(outer) {
     slave_in.b.bits.id := bId
 }
 
-trait HasPeripheryHLS${FUNC}AXI { this: BaseSubsystem =>
+trait CanHavePeripheryHLS${FUNC}AXI { this: BaseSubsystem =>
+    //implicit val p: Parameters
+
     private val address = BigInt(${BASE_ADDR})
     private val axi_m_portName = "HLS-Accelerator-${FUNC}-master"
     private val axilite_s_portName = "HLS-Accelerator-${FUNC}-slave"
 
+    // Disable Config 
+    //p(${FUNC}Key).map { k =>
+      
         //val accel_s_axi_width = ${S_AXI_DATA_WIDTH} 
         //val hls_${FUNC}_accel = LazyModule(new HLS${FUNC}AXI(address, sbus.beatBytes))
         val hls_${FUNC}_accel = LazyModule(new HLS${FUNC}AXI(address, ${S_AXI_DATA_WIDTH} >> 3))
@@ -77,8 +85,13 @@ trait HasPeripheryHLS${FUNC}AXI { this: BaseSubsystem =>
                              // Compared to TLWidthWidget, TLFragmenter saves the id info?
                              := TLFragmenter(${S_AXI_DATA_WIDTH} >> 3, 64, alwaysMin=true, holdFirstDeny=true))
         }
+    //}
 }
 
-trait HasPeripheryHLS${FUNC}AXIImp extends LazyModuleImp {
-    val outer: HasPeripheryHLS${FUNC}AXI
+trait CanHavePeripheryHLS${FUNC}AXIImp extends LazyModuleImp {
+    val outer: CanHavePeripheryHLS${FUNC}AXI
 }
+
+// class WithHLS${FUNC}() extends Config((site, here, up) => {
+//   case ${FUNC}Key => Some(${FUNC}Config())
+// })