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Tom Stellard b951f10701 AMDGPU/SI: Add support for spilling VGPRs without having to scavenge registers 
Summary:
When we are spilling SGPRs to scratch memory, we usually don't have
free SGPRs to do the address calculation, so we need to re-use the
ScratchOffset register for the calculation.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18917

llvm-svn: 266244
 		2016-04-13 20:44:16 +00:00
..
AsmParser [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status 2016-04-13 16:18:41 +00:00
Disassembler [AMDGPU] Disassembler: support for DPP 2016-03-31 14:15:04 +00:00
InstPrinter [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status 2016-04-13 16:18:41 +00:00
MCTargetDesc AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
Utils Make helper functions static. NFC. 2016-04-07 10:10:09 +00:00
AMDGPU.h AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPU.td AMDGPU: More bits of frame index are known to be zero 2016-02-27 20:26:57 +00:00
AMDGPUAlwaysInlinePass.cpp
…
AMDGPUAnnotateKernelFeatures.cpp AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr 2016-01-30 05:10:59 +00:00
AMDGPUAnnotateUniformValues.cpp AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
AMDGPUAsmPrinter.cpp [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status 2016-04-13 16:18:41 +00:00
AMDGPUAsmPrinter.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUCallingConv.td AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUFrameLowering.cpp AMDGPU: Fix old comments that mention AMDIL 2016-01-20 21:22:21 +00:00
AMDGPUFrameLowering.h
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AMDGPUISelDAGToDAG.cpp AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
AMDGPUISelLowering.cpp AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
AMDGPUISelLowering.h AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
AMDGPUInstrInfo.cpp AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cpp 2016-01-28 16:04:37 +00:00
AMDGPUInstrInfo.h AMDGPU: Add SIWholeQuadMode pass 2016-03-21 20:28:33 +00:00
AMDGPUInstrInfo.td AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2} 2016-04-01 18:27:37 +00:00
AMDGPUInstructions.td AMDGPU/SI: Implement atomic load/store for i32 and i64 2016-04-07 19:23:11 +00:00
AMDGPUIntrinsicInfo.cpp [llvm-tblgen] Avoid StringMatcher for GCC and MS builtin names 2016-01-27 01:43:12 +00:00
AMDGPUIntrinsicInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUIntrinsics.td AMDGPU: Remove bfi and bfm intrinsics 2016-02-08 19:06:01 +00:00
AMDGPUMCInstLower.cpp AMDGPU: Verify instructions in non-debug builds as well 2016-03-16 09:10:42 +00:00
AMDGPUMCInstLower.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUMachineFunction.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUMachineFunction.h AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp
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AMDGPUPromoteAlloca.cpp AMDGPU: Promote alloca should skip volatiles 2016-03-23 23:17:29 +00:00
AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUSubtarget.h AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUTargetMachine.cpp AMDGPU: Add SIWholeQuadMode pass 2016-03-21 20:28:33 +00:00
AMDGPUTargetMachine.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUTargetObjectFile.cpp AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA 2015-12-15 22:39:36 +00:00
AMDGPUTargetObjectFile.h AMDGPU/SI: Emit constant arrays in the .text section 2015-12-10 02:13:01 +00:00
AMDGPUTargetTransformInfo.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Partially implement getArithmeticInstrCost for FP ops 2016-03-25 01:00:32 +00:00
AMDILCFGStructurizer.cpp Bug 20810: Use report_fatal_error instead of unreachable 2016-03-02 03:33:55 +00:00
AMDKernelCodeT.h [AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields) 2016-02-24 10:54:25 +00:00
CIInstructions.td AMDGPU: Implement i64 global atomics 2016-04-12 14:05:11 +00:00
CMakeLists.txt AMDGPU: Add SIWholeQuadMode pass 2016-03-21 20:28:33 +00:00
CaymanInstructions.td AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
EvergreenInstructions.td AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
LLVMBuild.txt [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target 2016-02-18 03:42:32 +00:00
Processors.td AMDGPU/SI: Add Polaris support 2016-03-24 15:31:05 +00:00
R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
R600Defines.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600ISelLowering.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
R600ISelLowering.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600InstrFormats.td
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R600InstrInfo.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
R600InstrInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600Instructions.td AMDGPU: Rename intrinsic to better match instruction name 2016-02-13 01:03:00 +00:00
R600Intrinsics.td AMDGPU: Move AMDGPU intrinsics only used by R600 2016-01-26 04:49:24 +00:00
R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600MachineScheduler.cpp
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R600MachineScheduler.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp AMDGPU: Simplify boolean conditional return statements 2016-03-02 23:00:21 +00:00
R600RegisterInfo.cpp
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R600RegisterInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix 2016-01-22 19:00:09 +00:00
R700Instructions.td
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SIAnnotateControlFlow.cpp AMDGPU/SI: Fix a mis-compilation of multi-level breaks 2016-04-12 16:10:38 +00:00
SIDefines.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
SIFixControlFlowLiveIntervals.cpp
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SIFixSGPRCopies.cpp AMDGPU/SI: Fold operands with sub-registers 2016-01-07 17:10:29 +00:00
SIFixSGPRLiveRanges.cpp AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
SIFoldOperands.cpp AMDGPU: Fix passes depending on dominator tree for no reason 2016-02-11 06:15:34 +00:00
SIFrameLowering.cpp AMDGPU/SI: Don't try to move scratch wave offset when there are no free SGPRs 2016-03-03 03:45:09 +00:00
SIFrameLowering.h AMDGPU: Remove SIPrepareScratchRegs 2015-11-30 21:15:53 +00:00
SIISelLowering.cpp AMDGPU: Eliminate half of i64 or if one operand is zero_extend from i32 2016-04-12 18:24:38 +00:00
SIISelLowering.h AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
SIInsertNopsPass.cpp AMDGPU: Insert two S_NOP instructions for every high level source statement. 2016-03-03 03:53:29 +00:00
SIInsertWaits.cpp AMDGPU/SI: Insert wait states required after v_readfirstlane on SI 2016-04-12 18:40:43 +00:00
SIInstrFormats.td [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields. 2016-04-01 13:13:12 +00:00
SIInstrInfo.cpp AMDGPU/SI: Fix spilling of 96-bit registers 2016-04-12 23:57:30 +00:00
SIInstrInfo.h AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates 2016-04-07 14:47:07 +00:00
SIInstrInfo.td AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
SIInstructions.td AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics 2016-04-12 21:18:10 +00:00
SIIntrinsics.td AMDGPU: Remove old sample intrinsics 2016-01-26 04:38:08 +00:00
SILoadStoreOptimizer.cpp Test commit access 2016-03-29 15:15:44 +00:00
SILowerControlFlow.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
SILowerI1Copies.cpp AMDGPU: Fix passes depending on dominator tree for no reason 2016-02-11 06:15:34 +00:00
SIMachineFunctionInfo.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
SIMachineFunctionInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
SIMachineScheduler.cpp [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC. 2016-03-09 16:00:35 +00:00
SIMachineScheduler.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
SIRegisterInfo.cpp AMDGPU/SI: Add support for spilling VGPRs without having to scavenge registers 2016-04-13 20:44:16 +00:00
SIRegisterInfo.h AMDGPU/SI: Add support for spilling VGPRs without having to scavenge registers 2016-04-13 20:44:16 +00:00
SIRegisterInfo.td [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status 2016-04-13 16:18:41 +00:00
SISchedule.td AMDGPU/SI: Improve MachineSchedModel definition 2016-03-30 16:35:13 +00:00
SIShrinkInstructions.cpp AMDGPU: Materialize sign bits with bfrev 2016-03-11 07:42:49 +00:00
SITypeRewriter.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
SIWholeQuadMode.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
VIInstrFormats.td [AMDGPU] Fix SMEM instructions encoding/operand namings 2016-03-10 13:06:08 +00:00
VIInstructions.td [AMDGPU] Assembler: change v_madmk operands to have same order as mad. 2016-03-11 09:27:25 +00:00