AMDGPU: Partially implement getArithmeticInstrCost for FP ops
llvm-svn: 264374
This commit is contained in:
Matt Arsenault
parent
efe16c8eb4
commit
9651813ee0
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@ -29,6 +29,7 @@ using namespace llvm;
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#define DEBUG_TYPE "AMDGPUtti"
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void AMDGPUTTIImpl::getUnrollingPreferences(Loop *L,
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TTI::UnrollingPreferences &UP) {
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UP.Threshold = 300; // Twice the default.
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@ -84,6 +85,69 @@ unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
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return 64;
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}
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int AMDGPUTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
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TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo) {
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EVT OrigTy = TLI->getValueType(DL, Ty);
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if (!OrigTy.isSimple()) {
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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}
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// Legalize the type.
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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// Because we don't have any legal vector operations, but the legal types, we
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// need to account for split vectors.
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unsigned NElts = LT.second.isVector() ?
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LT.second.getVectorNumElements() : 1;
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MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy;
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switch (ISD) {
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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if (SLT == MVT::f64)
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return LT.first * NElts * get64BitInstrCost();
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if (SLT == MVT::f32 || SLT == MVT::f16)
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return LT.first * NElts * getFullRateInstrCost();
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break;
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case ISD::FDIV:
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case ISD::FREM:
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// FIXME: frem should be handled separately. The fdiv in it is most of it,
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// but the current lowering is also not entirely correct.
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if (SLT == MVT::f64) {
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int Cost = 4 * get64BitInstrCost() + 7 * getQuarterRateInstrCost();
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// Add cost of workaround.
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if (ST->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
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Cost += 3 * getFullRateInstrCost();
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return LT.first * Cost * NElts;
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}
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// Assuming no fp32 denormals lowering.
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if (SLT == MVT::f32 || SLT == MVT::f16) {
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assert(!ST->hasFP32Denormals() && "will change when supported");
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int Cost = 7 * getFullRateInstrCost() + 1 * getQuarterRateInstrCost();
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return LT.first * NElts * Cost;
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}
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break;
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default:
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break;
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}
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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}
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unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {
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// XXX - For some reason this isn't called for switch.
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switch (Opcode) {
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@ -21,9 +21,9 @@
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#include "AMDGPUTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class AMDGPUTargetLowering;
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class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
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typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT;
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@ -36,6 +36,28 @@ class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
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const AMDGPUSubtarget *getST() const { return ST; }
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const AMDGPUTargetLowering *getTLI() const { return TLI; }
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static inline int getFullRateInstrCost() {
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return TargetTransformInfo::TCC_Basic;
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}
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static inline int getHalfRateInstrCost() {
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return 2 * TargetTransformInfo::TCC_Basic;
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}
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// TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
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// should be 2 or 4.
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static inline int getQuarterRateInstrCost() {
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return 3 * TargetTransformInfo::TCC_Basic;
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}
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// On some parts, normal fp64 operations are half rate, and others
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// quarter. This also applies to some integer operations.
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inline int get64BitInstrCost() const {
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return ST->hasHalfRate64Ops() ?
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getHalfRateInstrCost() : getQuarterRateInstrCost();
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}
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public:
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explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const DataLayout &DL)
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: BaseT(TM, DL), ST(TM->getSubtargetImpl()),
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@ -61,6 +83,13 @@ public:
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unsigned getRegisterBitWidth(bool Vector);
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unsigned getMaxInterleaveFactor(unsigned VF);
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
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unsigned getCFInstrCost(unsigned Opcode);
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int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
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@ -0,0 +1,88 @@
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=+half-rate-64-ops < %s | FileCheck -check-prefix=FASTF64 -check-prefix=ALL %s
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefix=SLOWF64 -check-prefix=ALL %s
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; ALL: 'fadd_f32'
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; ALL: estimated cost of 1 for {{.*}} fadd float
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define void @fadd_f32(float addrspace(1)* %out, float addrspace(1)* %vaddr, float %b) #0 {
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%vec = load float, float addrspace(1)* %vaddr
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%add = fadd float %vec, %b
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store float %add, float addrspace(1)* %out
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ret void
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}
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; ALL: 'fadd_v2f32'
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; ALL: estimated cost of 2 for {{.*}} fadd <2 x float>
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define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
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%vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
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%add = fadd <2 x float> %vec, %b
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store <2 x float> %add, <2 x float> addrspace(1)* %out
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ret void
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}
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; ALL: 'fadd_v3f32'
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; ALL: estimated cost of 3 for {{.*}} fadd <3 x float>
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define void @fadd_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
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%vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
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%add = fadd <3 x float> %vec, %b
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store <3 x float> %add, <3 x float> addrspace(1)* %out
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ret void
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}
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; ALL: 'fadd_f64'
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; FASTF64: estimated cost of 2 for {{.*}} fadd double
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; SLOWF64: estimated cost of 3 for {{.*}} fadd double
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define void @fadd_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
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%vec = load double, double addrspace(1)* %vaddr
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%add = fadd double %vec, %b
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store double %add, double addrspace(1)* %out
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ret void
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}
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; ALL: 'fadd_v2f64'
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; FASTF64: estimated cost of 4 for {{.*}} fadd <2 x double>
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; SLOWF64: estimated cost of 6 for {{.*}} fadd <2 x double>
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define void @fadd_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %vaddr, <2 x double> %b) #0 {
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%vec = load <2 x double>, <2 x double> addrspace(1)* %vaddr
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%add = fadd <2 x double> %vec, %b
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store <2 x double> %add, <2 x double> addrspace(1)* %out
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ret void
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}
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; ALL: 'fadd_v3f64'
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; FASTF64: estimated cost of 6 for {{.*}} fadd <3 x double>
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; SLOWF64: estimated cost of 9 for {{.*}} fadd <3 x double>
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define void @fadd_v3f64(<3 x double> addrspace(1)* %out, <3 x double> addrspace(1)* %vaddr, <3 x double> %b) #0 {
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%vec = load <3 x double>, <3 x double> addrspace(1)* %vaddr
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%add = fadd <3 x double> %vec, %b
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store <3 x double> %add, <3 x double> addrspace(1)* %out
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ret void
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}
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; ALL 'fadd_f16'
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; ALL estimated cost of 1 for {{.*}} fadd half
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define void @fadd_f16(half addrspace(1)* %out, half addrspace(1)* %vaddr, half %b) #0 {
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%vec = load half, half addrspace(1)* %vaddr
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%add = fadd half %vec, %b
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store half %add, half addrspace(1)* %out
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ret void
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}
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; ALL 'fadd_v2f16'
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; ALL estimated cost of 2 for {{.*}} fadd <2 x half>
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define void @fadd_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr, <2 x half> %b) #0 {
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%vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr
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%add = fadd <2 x half> %vec, %b
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store <2 x half> %add, <2 x half> addrspace(1)* %out
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ret void
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}
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; ALL 'fadd_v4f16'
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; ALL estimated cost of 4 for {{.*}} fadd <4 x half>
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define void @fadd_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %vaddr, <4 x half> %b) #0 {
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%vec = load <4 x half>, <4 x half> addrspace(1)* %vaddr
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%add = fadd <4 x half> %vec, %b
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store <4 x half> %add, <4 x half> addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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@ -0,0 +1,96 @@
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii -mattr=+half-rate-64-ops < %s | FileCheck -check-prefix=ALL -check-prefix=CIFASTF64 %s
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=-half-rate-64-ops < %s | FileCheck -check-prefix=ALL -check-prefix=CISLOWF64 %s
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=tahiti -mattr=+half-rate-64-ops < %s | FileCheck -check-prefix=ALL -check-prefix=SIFASTF64 %s
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=verde -mattr=-half-rate-64-ops < %s | FileCheck -check-prefix=ALL -check-prefix=SISLOWF64 %s
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; CHECK: 'fdiv_f32'
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; ALL: estimated cost of 10 for {{.*}} fdiv float
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define void @fdiv_f32(float addrspace(1)* %out, float addrspace(1)* %vaddr, float %b) #0 {
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%vec = load float, float addrspace(1)* %vaddr
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%add = fdiv float %vec, %b
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store float %add, float addrspace(1)* %out
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ret void
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}
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; ALL: 'fdiv_v2f32'
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; ALL: estimated cost of 20 for {{.*}} fdiv <2 x float>
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define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
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%vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
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%add = fdiv <2 x float> %vec, %b
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store <2 x float> %add, <2 x float> addrspace(1)* %out
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ret void
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}
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; ALL: 'fdiv_v3f32'
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; ALL: estimated cost of 30 for {{.*}} fdiv <3 x float>
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define void @fdiv_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
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%vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
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%add = fdiv <3 x float> %vec, %b
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store <3 x float> %add, <3 x float> addrspace(1)* %out
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ret void
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}
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; ALL: 'fdiv_f64'
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; CIFASTF64: estimated cost of 29 for {{.*}} fdiv double
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; CISLOWF64: estimated cost of 33 for {{.*}} fdiv double
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; SIFASTF64: estimated cost of 32 for {{.*}} fdiv double
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; SISLOWF64: estimated cost of 36 for {{.*}} fdiv double
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define void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
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%vec = load double, double addrspace(1)* %vaddr
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%add = fdiv double %vec, %b
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store double %add, double addrspace(1)* %out
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ret void
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}
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; ALL: 'fdiv_v2f64'
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; CIFASTF64: estimated cost of 58 for {{.*}} fdiv <2 x double>
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; CISLOWF64: estimated cost of 66 for {{.*}} fdiv <2 x double>
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; SIFASTF64: estimated cost of 64 for {{.*}} fdiv <2 x double>
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; SISLOWF64: estimated cost of 72 for {{.*}} fdiv <2 x double>
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define void @fdiv_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %vaddr, <2 x double> %b) #0 {
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%vec = load <2 x double>, <2 x double> addrspace(1)* %vaddr
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%add = fdiv <2 x double> %vec, %b
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store <2 x double> %add, <2 x double> addrspace(1)* %out
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ret void
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}
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; ALL: 'fdiv_v3f64'
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; CIFASTF64: estimated cost of 87 for {{.*}} fdiv <3 x double>
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; CISLOWF64: estimated cost of 99 for {{.*}} fdiv <3 x double>
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; SIFASTF64: estimated cost of 96 for {{.*}} fdiv <3 x double>
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; SISLOWF64: estimated cost of 108 for {{.*}} fdiv <3 x double>
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define void @fdiv_v3f64(<3 x double> addrspace(1)* %out, <3 x double> addrspace(1)* %vaddr, <3 x double> %b) #0 {
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%vec = load <3 x double>, <3 x double> addrspace(1)* %vaddr
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%add = fdiv <3 x double> %vec, %b
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store <3 x double> %add, <3 x double> addrspace(1)* %out
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ret void
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}
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; ALL: 'fdiv_f16'
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; ALL: estimated cost of 10 for {{.*}} fdiv half
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define void @fdiv_f16(half addrspace(1)* %out, half addrspace(1)* %vaddr, half %b) #0 {
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%vec = load half, half addrspace(1)* %vaddr
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%add = fdiv half %vec, %b
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store half %add, half addrspace(1)* %out
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ret void
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}
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; ALL: 'fdiv_v2f16'
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; ALL: estimated cost of 20 for {{.*}} fdiv <2 x half>
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define void @fdiv_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr, <2 x half> %b) #0 {
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%vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr
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%add = fdiv <2 x half> %vec, %b
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store <2 x half> %add, <2 x half> addrspace(1)* %out
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ret void
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}
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; ALL: 'fdiv_v4f16'
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; ALL: estimated cost of 40 for {{.*}} fdiv <4 x half>
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define void @fdiv_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %vaddr, <4 x half> %b) #0 {
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%vec = load <4 x half>, <4 x half> addrspace(1)* %vaddr
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%add = fdiv <4 x half> %vec, %b
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store <4 x half> %add, <4 x half> addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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@ -0,0 +1,88 @@
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=+half-rate-64-ops < %s | FileCheck -check-prefix=FASTF64 -check-prefix=ALL %s
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefix=SLOWF64 -check-prefix=ALL %s
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; ALL: 'fmul_f32'
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; ALL: estimated cost of 1 for {{.*}} fmul float
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define void @fmul_f32(float addrspace(1)* %out, float addrspace(1)* %vaddr, float %b) #0 {
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%vec = load float, float addrspace(1)* %vaddr
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%add = fmul float %vec, %b
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store float %add, float addrspace(1)* %out
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ret void
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}
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; ALL: 'fmul_v2f32'
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; ALL: estimated cost of 2 for {{.*}} fmul <2 x float>
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define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
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%vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
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%add = fmul <2 x float> %vec, %b
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store <2 x float> %add, <2 x float> addrspace(1)* %out
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ret void
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}
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; ALL: 'fmul_v3f32'
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; ALL: estimated cost of 3 for {{.*}} fmul <3 x float>
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define void @fmul_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
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%vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
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%add = fmul <3 x float> %vec, %b
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store <3 x float> %add, <3 x float> addrspace(1)* %out
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ret void
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}
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; ALL: 'fmul_f64'
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; FASTF64: estimated cost of 2 for {{.*}} fmul double
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; SLOWF64: estimated cost of 3 for {{.*}} fmul double
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define void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
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%vec = load double, double addrspace(1)* %vaddr
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%add = fmul double %vec, %b
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store double %add, double addrspace(1)* %out
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ret void
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}
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; ALL: 'fmul_v2f64'
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; FASTF64: estimated cost of 4 for {{.*}} fmul <2 x double>
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; SLOWF64: estimated cost of 6 for {{.*}} fmul <2 x double>
|
||||
define void @fmul_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %vaddr, <2 x double> %b) #0 {
|
||||
%vec = load <2 x double>, <2 x double> addrspace(1)* %vaddr
|
||||
%add = fmul <2 x double> %vec, %b
|
||||
store <2 x double> %add, <2 x double> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fmul_v3f64'
|
||||
; FASTF64: estimated cost of 6 for {{.*}} fmul <3 x double>
|
||||
; SLOWF64: estimated cost of 9 for {{.*}} fmul <3 x double>
|
||||
define void @fmul_v3f64(<3 x double> addrspace(1)* %out, <3 x double> addrspace(1)* %vaddr, <3 x double> %b) #0 {
|
||||
%vec = load <3 x double>, <3 x double> addrspace(1)* %vaddr
|
||||
%add = fmul <3 x double> %vec, %b
|
||||
store <3 x double> %add, <3 x double> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL 'fmul_f16'
|
||||
; ALL estimated cost of 1 for {{.*}} fmul half
|
||||
define void @fmul_f16(half addrspace(1)* %out, half addrspace(1)* %vaddr, half %b) #0 {
|
||||
%vec = load half, half addrspace(1)* %vaddr
|
||||
%add = fmul half %vec, %b
|
||||
store half %add, half addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL 'fmul_v2f16'
|
||||
; ALL estimated cost of 2 for {{.*}} fmul <2 x half>
|
||||
define void @fmul_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr, <2 x half> %b) #0 {
|
||||
%vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr
|
||||
%add = fmul <2 x half> %vec, %b
|
||||
store <2 x half> %add, <2 x half> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL 'fmul_v4f16'
|
||||
; ALL estimated cost of 4 for {{.*}} fmul <4 x half>
|
||||
define void @fmul_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %vaddr, <4 x half> %b) #0 {
|
||||
%vec = load <4 x half>, <4 x half> addrspace(1)* %vaddr
|
||||
%add = fmul <4 x half> %vec, %b
|
||||
store <4 x half> %add, <4 x half> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=+half-rate-64-ops < %s | FileCheck -check-prefix=FASTF64 -check-prefix=ALL %s
|
||||
; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefix=SLOWF64 -check-prefix=ALL %s
|
||||
|
||||
; ALL: 'fsub_f32'
|
||||
; ALL: estimated cost of 1 for {{.*}} fsub float
|
||||
define void @fsub_f32(float addrspace(1)* %out, float addrspace(1)* %vaddr, float %b) #0 {
|
||||
%vec = load float, float addrspace(1)* %vaddr
|
||||
%add = fsub float %vec, %b
|
||||
store float %add, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fsub_v2f32'
|
||||
; ALL: estimated cost of 2 for {{.*}} fsub <2 x float>
|
||||
define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
|
||||
%vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
|
||||
%add = fsub <2 x float> %vec, %b
|
||||
store <2 x float> %add, <2 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fsub_v3f32'
|
||||
; ALL: estimated cost of 3 for {{.*}} fsub <3 x float>
|
||||
define void @fsub_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
|
||||
%vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
|
||||
%add = fsub <3 x float> %vec, %b
|
||||
store <3 x float> %add, <3 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fsub_f64'
|
||||
; FASTF64: estimated cost of 2 for {{.*}} fsub double
|
||||
; SLOWF64: estimated cost of 3 for {{.*}} fsub double
|
||||
define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
|
||||
%vec = load double, double addrspace(1)* %vaddr
|
||||
%add = fsub double %vec, %b
|
||||
store double %add, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fsub_v2f64'
|
||||
; FASTF64: estimated cost of 4 for {{.*}} fsub <2 x double>
|
||||
; SLOWF64: estimated cost of 6 for {{.*}} fsub <2 x double>
|
||||
define void @fsub_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %vaddr, <2 x double> %b) #0 {
|
||||
%vec = load <2 x double>, <2 x double> addrspace(1)* %vaddr
|
||||
%add = fsub <2 x double> %vec, %b
|
||||
store <2 x double> %add, <2 x double> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fsub_v3f64'
|
||||
; FASTF64: estimated cost of 6 for {{.*}} fsub <3 x double>
|
||||
; SLOWF64: estimated cost of 9 for {{.*}} fsub <3 x double>
|
||||
define void @fsub_v3f64(<3 x double> addrspace(1)* %out, <3 x double> addrspace(1)* %vaddr, <3 x double> %b) #0 {
|
||||
%vec = load <3 x double>, <3 x double> addrspace(1)* %vaddr
|
||||
%add = fsub <3 x double> %vec, %b
|
||||
store <3 x double> %add, <3 x double> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fsub_f16'
|
||||
; ALL: estimated cost of 1 for {{.*}} fsub half
|
||||
define void @fsub_f16(half addrspace(1)* %out, half addrspace(1)* %vaddr, half %b) #0 {
|
||||
%vec = load half, half addrspace(1)* %vaddr
|
||||
%add = fsub half %vec, %b
|
||||
store half %add, half addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fsub_v2f16'
|
||||
; ALL: estimated cost of 2 for {{.*}} fsub <2 x half>
|
||||
define void @fsub_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr, <2 x half> %b) #0 {
|
||||
%vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr
|
||||
%add = fsub <2 x half> %vec, %b
|
||||
store <2 x half> %add, <2 x half> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL: 'fsub_v4f16'
|
||||
; ALL: estimated cost of 4 for {{.*}} fsub <4 x half>
|
||||
define void @fsub_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %vaddr, <4 x half> %b) #0 {
|
||||
%vec = load <4 x half>, <4 x half> addrspace(1)* %vaddr
|
||||
%add = fsub <4 x half> %vec, %b
|
||||
store <4 x half> %add, <4 x half> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue