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InstPrinter
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MCTargetDesc
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TargetInfo
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AMDGPU.h
R600/SI: Use VSrc_* register classes as the default classes for types
2013-08-06 23:08:28 +00:00
AMDGPU.td
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AMDGPUAsmPrinter.cpp
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AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
R600/SI: Fix an obvious typo
2013-08-14 22:22:03 +00:00
AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUISelDAGToDAG.cpp
R600/SI: Use VSrc_* register classes as the default classes for types
2013-08-06 23:08:28 +00:00
AMDGPUISelLowering.cpp
R600: Implement TargetLowering::getVectorIdxTy()
2013-08-05 22:22:07 +00:00
AMDGPUISelLowering.h
R600: Implement TargetLowering::getVectorIdxTy()
2013-08-05 22:22:07 +00:00
AMDGPUIndirectAddressing.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
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AMDGPUInstructions.td
R600: Add support for 24-bit MUL instructions
2013-07-23 01:48:42 +00:00
AMDGPUIntrinsics.td
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AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPUMachineFunction.cpp
Move string pointer from being a static class member to just a static global in the one file its needed in.
2013-07-17 00:31:35 +00:00
AMDGPUMachineFunction.h
Move string pointer from being a static class member to just a static global in the one file its needed in.
2013-07-17 00:31:35 +00:00
AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
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AMDGPUSubtarget.h
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AMDGPUTargetMachine.cpp
R600/SI: Use VSrc_* register classes as the default classes for types
2013-08-06 23:08:28 +00:00
AMDGPUTargetMachine.h
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 00:01:07 +00:00
AMDGPUTargetTransformInfo.cpp
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 00:01:07 +00:00
AMDILBase.td
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AMDILCFGStructurizer.cpp
R600: Remove predicated_break inst
2013-07-31 19:31:14 +00:00
AMDILISelLowering.cpp
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILRegisterInfo.td
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CMakeLists.txt
R600: Add new file from r187831 to CMakeLists.txt
2013-08-06 23:12:34 +00:00
LLVMBuild.txt
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Makefile
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Processors.td
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R600ControlFlowFinalizer.cpp
R600: Add 64-bit float load/store support
2013-08-01 15:23:42 +00:00
R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
R600: Remove predicated_break inst
2013-07-31 19:31:14 +00:00
R600ISelLowering.cpp
R600: Set scheduling preference to Sched::Source
2013-08-12 22:33:21 +00:00
R600ISelLowering.h
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R600InstrFormats.td
Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
2013-07-31 20:43:03 +00:00
R600InstrInfo.cpp
R600: Add 64-bit float load/store support
2013-08-01 15:23:42 +00:00
R600InstrInfo.h
Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
2013-07-31 20:43:03 +00:00
R600Instructions.td
R600/SI: Handle MSAA texture targets
2013-08-14 22:22:14 +00:00
R600Intrinsics.td
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
Revert "R600: Non vector only instruction can be scheduled on trans unit"
2013-07-31 20:43:27 +00:00
R600MachineScheduler.h
Revert "R600: Non vector only instruction can be scheduled on trans unit"
2013-07-31 20:43:27 +00:00
R600OptimizeVectorRegisters.cpp
R600: Do not mergevector after a vector reg is used
2013-07-31 19:32:12 +00:00
R600Packetizer.cpp
Revert "R600: Non vector only instruction can be scheduled on trans unit"
2013-07-31 20:43:27 +00:00
R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
R600: Add 64-bit float load/store support
2013-08-01 15:23:42 +00:00
R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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SIAnnotateControlFlow.cpp
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SIDefines.h
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
2013-08-14 23:24:17 +00:00
SIFixSGPRCopies.cpp
R600/SI: Use VSrc_* register classes as the default classes for types
2013-08-06 23:08:28 +00:00
SIISelLowering.cpp
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
2013-08-14 23:24:17 +00:00
SIISelLowering.h
R600/SI: FMA is faster than fmul and fadd for f64
2013-08-10 10:38:54 +00:00
SIInsertWaits.cpp
Initialize SIInsertWaits::ExpInstrTypesSeen in the pass constructor.
2013-08-07 07:47:41 +00:00
SIInstrFormats.td
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
2013-08-14 23:24:17 +00:00
SIInstrInfo.cpp
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
2013-08-14 23:24:17 +00:00
SIInstrInfo.h
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
2013-08-14 23:24:17 +00:00
SIInstrInfo.td
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
2013-08-14 23:24:17 +00:00
SIInstructions.td
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
2013-08-14 23:24:17 +00:00
SIIntrinsics.td
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SILowerControlFlow.cpp
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
R600/SI: Add more special cases for opcodes to ensureSRegLimit()
2013-08-06 23:08:18 +00:00
SIRegisterInfo.h
R600/SI: Add more special cases for opcodes to ensureSRegLimit()
2013-08-06 23:08:18 +00:00
SIRegisterInfo.td
R600/SI: Allow conversion between v32i8 and v8i32
2013-08-14 22:22:09 +00:00
SISchedule.td
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