Commit Graph

258870 Commits

Author SHA1 Message Date
Rui Ueyama ea93fe00b9 Inline small functions that are used only once as lambdas.
llvm-svn: 299494
2017-04-05 00:43:25 +00:00
Rui Ueyama 5f20b6304b Add newlines.
llvm-svn: 299493
2017-04-05 00:43:05 +00:00
Rui Ueyama a08fa2eca3 Make dummy variable's scope smaller.
llvm-svn: 299492
2017-04-05 00:42:45 +00:00
Bob Haarman 6de8134784 ThinLTOBitcodeWriter: handle aliases first in filterModule
Summary: This change fixes a "local linkage requires default visibility" assert when attempting to build LLVM with ThinLTO on Windows.

Reviewers: pcc, tejohnson, mehdi_amini

Reviewed By: pcc

Subscribers: llvm-commits, Prazek

Differential Revision: https://reviews.llvm.org/D31632

llvm-svn: 299491
2017-04-05 00:42:07 +00:00
Ahmed Bougacha ec8b1fb539 [X86] Relax assert in broadcast-of-subvector lowering.
Before r294774, there was a problem when lowering broadcasts to use
128-bit subvectors.

When we looked through a bitcast to find the broadcast input, we'd keep
using the original type, so you'd end up with things like:
  (v8f32 (broadcast
    (v4f32 (extract_subvector
      (v8i32 V),
      ...))
    ))

r294774 fixed it to always emit subvectors with the scalar type of the
original source.

It also introduced some asserts, to check that we use scalars with
the same size, and vectors with the same number of elements.

The scalar size equality is checked earlier when looking through bitcasts,
and is a useful assert.

However, the number of elements don't have to be identical: we're always
going to extract a 128-bit subvector, and we can have different size
inputs if we looked through a concat_vector to find a 256-bit source.

Relax the overzealous assert.

Replace it with a check of the original source vector being 256 or 512
bits.  If it's 128 bits, we can't extract_subvector from it.

Fixes PR32371.

llvm-svn: 299490
2017-04-05 00:14:39 +00:00
Jim Ingham 9645a6290a Reverting r299374 & r299402 due to testsuite failure.
This caused a failure in the test case:

  functionalities/breakpoint/objc/TestObjCBreakpoints.py

When we are parsing up names we stick interesting parts of the names
in various buckets, one of which is the ObjC selector bucket.  The new
C++ name parser must be interfering with this process somehow.

<rdar://problem/31439305>

llvm-svn: 299489
2017-04-05 00:08:21 +00:00
Adam Nemet d7f9511041 Another attempt to fix the sphinx warning from r299470
llvm-svn: 299488
2017-04-04 23:46:34 +00:00
Matt Arsenault 7b0d947404 Allow targets to opt-in to codegen in SCC order
Decouple this setting from EnableIRPA.

To support function calls on AMDGPU, it is necessary to
report the global register usage throughout the kernel's
call graph, so callees need to be handled first.

llvm-svn: 299487
2017-04-04 23:44:46 +00:00
Daniel Berlin e33bc31df4 Re-apply MemorySSA: Add support for caching clobbering access in
stores with some fixes.

Summary:
This enables us to cache the clobbering access for stores, despite the
fact that we can't rewrite the use-def chains themselves.

Early testing shows that, after this change, for larger testcases, it
will be a significant net positive (memory and time) to remove the
walker caching.

Reviewers: george.burgess.iv, davide

Subscribers: Prazek, llvm-commits

Differential Revision: https://reviews.llvm.org/D31567

llvm-svn: 299486
2017-04-04 23:43:10 +00:00
Daniel Berlin f49d4c45a1 Revert "MemorySSA: Add support for caching clobbering access in stores"
This reverts revision r299322.

llvm-svn: 299485
2017-04-04 23:43:04 +00:00
Petr Hosek 880cfd45fc [MC] Set defaults based on section names and support name suffixes
Set correct default flags and section type based on its name for .text,
.data, .bss, .init_array, .fini_array, .preinit_array, .tdata, and .tbss
and support section name suffixes for .data.*, .rodata.*, .text.*,
.bss.*, .tdata.* and .tbss.* which matches the behavior of GAS.

Fixes PR31888.

Differential Revision: https://reviews.llvm.org/D30229

llvm-svn: 299484
2017-04-04 23:32:45 +00:00
Ahmed Bougacha d3c03a5ddd [AArch64] Avoid partial register deps on insertelt of load into lane 0.
This improves upon r246462: that prevented FMOVs from being emitted
for the cross-class INSERT_SUBREGs by disabling the formation of
INSERT_SUBREGs of LOAD.  But the ld1.s that we started selecting
caused us to introduce partial dependencies on the vector register.

Avoid that by using SCALAR_TO_VECTOR: it's a first-class citizen that
is folded away by many patterns, including the scalar LDRS that we
want in this case.

Credit goes to Adam for finding the issue!

llvm-svn: 299482
2017-04-04 22:55:53 +00:00
Adam Nemet e73e00c9b2 Fix sphinx warning from r299470
llvm-svn: 299481
2017-04-04 22:45:20 +00:00
Evgeniy Stepanov 1df7d9b60b Change section flag character for SHF_LINK_ORDER to "o".
See matching MC change in https://reviews.llvm.org/D31554.

llvm-svn: 299480
2017-04-04 22:35:16 +00:00
Evgeniy Stepanov 12de7b2446 Change section flag character for SHF_LINK_ORDER to "o".
GAS uses "m" as a compatibility alias for "M" (SHF_MERGE).

"o" is free, except on ia64, where it already means SHF_LINK_ORDER.

llvm-svn: 299479
2017-04-04 22:35:08 +00:00
Rafael Espindola 69a9e931ce Avoid calling basename to compute xdynamiclib_namespec.
This also exposes a xdynamiclib_filename that can be used to simplify
a few tests.

llvm-svn: 299478
2017-04-04 22:33:02 +00:00
Craig Topper 1534495ffd [InstCombine] Add test cases for various add/subtracts of constants(scalar, splat, and vector) with phis and selects. Improvements coming in a future commit.
llvm-svn: 299476
2017-04-04 22:22:30 +00:00
Rafael Espindola 07503baf3a [lit] Add a minimum export implementation.
llvm-svn: 299475
2017-04-04 22:20:18 +00:00
Sanjay Patel 0bf0abedf6 [InstCombine] rename variable for easier reading; NFC
We usually give constants a 'C' somewhere in the name...

llvm-svn: 299474
2017-04-04 22:06:03 +00:00
Meador Inge 51208a38de [Driver] Add option to print the resource directory
This patch adds the option -print-resource-dir. It simply
prints the resource directory. This information will eventually
be used in compiler-rt to setup COMPILER_RT_LIBRARY_INSTALL_DIR.

Patch by Catherine Moore!

Differential Revision: https://reviews.llvm.org/D31447

llvm-svn: 299473
2017-04-04 21:46:50 +00:00
Craig Topper c745b6a1f6 [InstCombine] Turn subtract of vectors of i1 into xor like we do for scalar i1. Matches what we already do for add.
llvm-svn: 299472
2017-04-04 21:44:56 +00:00
Rafael Espindola f58991b7a4 Don't remove the cwd.
This works with a regular shell since the kernel can keep track of a
deleted cwd. Since we just keep a path string, the following
subprocess invocations fail.

I think this would also fail on windows.

llvm-svn: 299471
2017-04-04 21:42:59 +00:00
Adam Nemet 60d3264d5f Add #pragma clang fp
This adds the new pragma and the first variant, contract(on/off/fast).

The pragma has the same block scope rules as STDC FP_CONTRACT, i.e. it can be
placed at the beginning of a compound statement or at file scope.

Similarly to STDC FP_CONTRACT there is no need to use attributes.  First an
annotate token is inserted with the parsed details of the pragma.  Then the
annotate token is parsed in the proper contexts and the Sema is updated with
the corresponding FPOptions using the shared ActOn function with STDC
FP_CONTRACT.

After this the FPOptions from the Sema is propagated into the AST expression
nodes.  There is no change here.

I was going to add a 'default' option besides 'on/off/fast' similar to STDC
FP_CONTRACT but then decided against it. I think that we'd have to make option
uppercase then to avoid using 'default' the keyword.  Also because of the
scoped activation of pragma I am not sure there is really a need a for this.

Differential Revision: https://reviews.llvm.org/D31276

llvm-svn: 299470
2017-04-04 21:18:36 +00:00
Adam Nemet 370d0877f6 Set FMF for -ffp-contract=fast
With this, FMF(contract) becomes an alternative way to express the request to
contract.

These are currently only propagated for FMul, FAdd and FSub.  The rest will be
added as more FMFs are hooked up for this.

This is toward fixing PR25721.

Differential Revision: https://reviews.llvm.org/D31168

llvm-svn: 299469
2017-04-04 21:18:30 +00:00
Balaram Makam b3120b6d3f [AArch64] Add missing schedinfo, check completeness for Falkor.
llvm-svn: 299468
2017-04-04 21:15:53 +00:00
Keno Fischer 282c62495f [ExecutionDepsFix] Don't revisit true dependencies
If an instruction has a true dependency, it makes sense for to use that
register for any undef read operands in the same instruction (we'll have
to wait for that register to become available anyway). This logic
was already implemented. However, the code would then still try to
revisit that instruction and break the dependency (and always fail,
since by definition a true dependency has to be live before the
instruction). Avoid revisiting such instructions as a performance
optimization. No functional change.

Differential Revision: https://reviews.llvm.org/D30173

llvm-svn: 299467
2017-04-04 20:30:47 +00:00
Craig Topper 86173600ec [InstCombine] Support folding and/or/xor with a constant vector RHS into selects and phis
Currently we only fold with ConstantInt RHS. This generalizes to any Constant RHS.

Differential Revision: https://reviews.llvm.org/D31610

llvm-svn: 299466
2017-04-04 20:26:25 +00:00
Matthias Gehre ddae2516b8 [clang-format] fix crash in NamespaceEndCommentsFixer (PR32438)
Summary:
The new test case was crashing before. Now it passes
as expected.

Reviewers: djasper

Subscribers: klimek, cfe-commits

Differential Revision: https://reviews.llvm.org/D31441

llvm-svn: 299465
2017-04-04 20:11:13 +00:00
Rafael Espindola 8465d08392 Don't resolve hidden undef to a DSO.
The ELF spec says:

all of the non-default visibility attributes, when applied to a symbol
reference, imply that a definition to satisfy that reference must be
provided within the current executable or shared object.

But we were trying to resolve those undef references to shared
symbols. That causes odd results like creating a got entry with
a relocation pointing to 0.

llvm-svn: 299464
2017-04-04 20:03:34 +00:00
Dominic Chen 08f943c563 [analyzer] Add new Z3 constraint manager backend
Summary: Implement new Z3 constraint manager backend.

Reviewers: zaks.anna, dcoughlin, NoQ, xazax.hun

Subscribers: mgorny, cfe-commits

Differential Revision: https://reviews.llvm.org/D28952

llvm-svn: 299463
2017-04-04 19:52:25 +00:00
Petr Hosek 9eb0a1e09b [AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia
This mode is just like -mcmodel=small except that it moves the
thread pointer from TPIDR_EL0 to TPIDR_EL1.

Patch by Roland McGrath.

Differential Revision: https://reviews.llvm.org/D31624

llvm-svn: 299462
2017-04-04 19:51:53 +00:00
Jonas Devlieghere c45b03bddc [clangd] Link against clangSema
Fixes linking issue introduced by rL299421 when building LLVM with
shared libraries.

llvm-svn: 299461
2017-04-04 19:42:29 +00:00
Craig Topper 11791a723b [InstCombine] Add test cases for missing combines of phis with and/or/xor with constant argument. NFC
llvm-svn: 299460
2017-04-04 19:31:21 +00:00
Coby Tayree b76fb84032 [fixup][X86][inline-asm] Add support for MS 'EVEN' directive
refining tested targets resolution, to amend failures caused by rL299454

llvm-svn: 299459
2017-04-04 19:20:21 +00:00
Yi Kong 57019dc9b2 Implement host CPU detection for AArch64
This shares detection logic with ARM(32), since AArch64 capable CPUs may
also run in 32-bit system mode.

We observe weird /proc/cpuinfo output for MSM8992 and MSM8994, where
they report all CPU cores as one single model, depending on which CPU
core the kernel is running on. As a workaround, we hardcode the known
CPU part name for these SoCs.

For big.LITTLE systems, this patch would only return the part name of
the first core (usually the little core). Proper support will be added
in a follow-up change.

Differential Revision: D31675

llvm-svn: 299458
2017-04-04 19:06:04 +00:00
Matt Arsenault 3333968771 Verifier: Check some amdgpu calling convention restrictions
llvm-svn: 299457
2017-04-04 18:43:11 +00:00
Balaram Makam 7b5c098cfa [AArch64] Refine Falkor Machine Model - Part 2
llvm-svn: 299456
2017-04-04 18:42:14 +00:00
Coby Tayree b186493cc8 [X86][inline-asm] Add support for MS 'EVEN' directive
MS assembly syntax provide us with the 'EVEN' directive as a synonymous to at&t '.even'.
This patch include the (small, simple) changes need to allow it.

llvm-side:
https://reviews.llvm.org/D27417

Differential Revision: https://reviews.llvm.org/D27418

llvm-svn: 299454
2017-04-04 17:58:28 +00:00
Coby Tayree 3847be9410 [X86][inline-asm] Add support for MS 'EVEN' directive
MS assembly syntax provide us with the 'EVEN' directive as a synonymous to at&t '.even'.
This patch include the (small, simple) changes need to allow it.

Test is provided at the following (clang-side) review:
https://reviews.llvm.org/D27418

Differential Revision: https://reviews.llvm.org/D27417

llvm-svn: 299453
2017-04-04 17:57:23 +00:00
Rafael Espindola 01a8db64b1 Avoid sub shell.
Another step in getting these tests to run with the integrated one.

llvm-svn: 299452
2017-04-04 17:49:45 +00:00
Jim Ingham 61cc47ad30 Tone down the "lldb types" log a bit.
Change the get shared class info function to only
dump its results to the inferior stdout when the
log is verbose.  This matches the lldb side of the
same process, which only logs what it found if the
log is on verbose.

llvm-svn: 299451
2017-04-04 17:48:21 +00:00
Craig Topper 78cfbc1635 [InstCombine] Add more test cases for missing combines of selects with and/or/xor with constant argument. NFC
llvm-svn: 299450
2017-04-04 17:48:08 +00:00
Lang Hames d22badef45 [RuntimeDyld] Make RuntimeDyld honor the ProcessAllSections flag.
When the ProcessAllSections flag (introduced in r204398) is set RuntimeDyld is
supposed to make a call to the client's memory manager for every section in each
object that is loaded. Due to some missing checks, this was not happening in all
cases. This patch adds the missing cases, and fixes the Orc unit test that
verifies correct behavior for ProcessAllSections (The unit test had been
silently bailing out due to an ordering issue: a change in the test order meant
that this unit-test was running before the native target was registered. This
issue has also been fixed in this patch).

This fixes <rdar://problem/22789965>

llvm-svn: 299449
2017-04-04 17:03:49 +00:00
Sanjay Patel ac618383e3 [x86] remove dead select-of-constants transform; NFCI
https://reviews.llvm.org/D30537 / https://reviews.llvm.org/rL296977 added these transforms
and other related transforms to the generic DAGCombiner (with a hook that x86 sets to true),
so these patterns should not exist by the time we reach the target-specific combiner hook.

llvm-svn: 299448
2017-04-04 16:54:58 +00:00
Anastasia Stulova 297908da5b [Bug 25404] Fix crash on typedef in OpenCL 2.0
Fixed the assertion due to absence of source location for
implicitly defined types (using addImplicitTypedef()).
During Sema checks the source location is being expected
and therefore an assertion is triggered.

The change is not specific to OpenCL. But it is particularly
common for OpenCL types to be declared implicitly in Clang
to support the mode without the standard header.

Differential Revision: https://reviews.llvm.org/D31397

llvm-svn: 299447
2017-04-04 16:50:46 +00:00
Rong Xu 48596b6f7a [PGO] Memory intrinsic calls optimization based on profiled size
This patch optimizes two memory intrinsic operations: memset and memcpy based
on the profiled size of the operation. The high level transformation is like:
  mem_op(..., size)
  ==>
  switch (size) {
    case s1:
       mem_op(..., s1);
       goto merge_bb;
    case s2:
       mem_op(..., s2);
       goto merge_bb;
    ...
    default:
       mem_op(..., size);
       goto merge_bb;
    }
  merge_bb:

Differential Revision: http://reviews.llvm.org/D28966

llvm-svn: 299446
2017-04-04 16:42:20 +00:00
Jin-Gu Kang e7cdcdea73 Preserve vec3 type.
Summary: Preserve vec3 type with CodeGen option.

Reviewers: Anastasia, bruno

Reviewed By: Anastasia

Subscribers: bruno, ahatanak, cfe-commits

Differential Revision: https://reviews.llvm.org/D30810

llvm-svn: 299445
2017-04-04 16:40:25 +00:00
Matt Arsenault 3e90f84806 AMDGPU: Remove legacy export intrinsic
llvm-svn: 299444
2017-04-04 16:34:39 +00:00
Matt Arsenault 236da200f1 AMDGPU: Remove legacy image intrinsics
llvm-svn: 299443
2017-04-04 16:34:35 +00:00
Michael Zuckerman 13bcf4944a Fix problem with test.
llvm-svn: 299442
2017-04-04 15:44:06 +00:00