ed6184aef2
Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
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llvm-svn: 27150
2006-03-26 09:53:12 +00:00
2bc0941e2a
Build arbitrary vector with more than 2 distinct scalar elements with a
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series of unpack and interleave ops.
llvm-svn: 27119
2006-03-25 09:37:23 +00:00
79e500ec74
Added SSE cachebility ops
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llvm-svn: 27103
2006-03-25 06:03:26 +00:00
6f7d31ea50
Added 128-bit packed integer subtraction.
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llvm-svn: 27096
2006-03-25 01:33:37 +00:00
980c4d5b46
Added CVTSS2SI.
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llvm-svn: 27094
2006-03-25 01:00:18 +00:00
e7ee6a5e32
Support for scalar to vector with zero extension.
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llvm-svn: 27091
2006-03-24 23:15:12 +00:00
2f0277bf48
Added LDMXCSR
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llvm-svn: 27087
2006-03-24 22:28:37 +00:00
97599f1211
plug the intrinsics into the patterns for movmsk*
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llvm-svn: 27083
2006-03-24 21:49:18 +00:00
082c8785ef
Handle BUILD_VECTOR with all zero elements.
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llvm-svn: 27056
2006-03-24 07:29:27 +00:00
2595a687da
More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
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llvm-svn: 27040
2006-03-24 02:58:06 +00:00
d27fb3e85e
Handle more shuffle cases with SHUFP* instructions.
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llvm-svn: 27024
2006-03-24 01:18:28 +00:00
82ed4a42f9
Following icc's lead: use movdqa to load / store 128-bit integer vectors
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llvm-svn: 26980
2006-03-23 07:44:07 +00:00
7055878170
Add v4i32 <-> v4f32 bitconvert patterns.
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llvm-svn: 26969
2006-03-23 02:36:37 +00:00
b9b0550dc6
Add 128-bit integer vector load and add (for testing).
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llvm-svn: 26967
2006-03-23 01:57:24 +00:00
ed794cd27b
SHUFP* are two address code.
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llvm-svn: 26959
2006-03-22 20:08:18 +00:00
d4e1557941
- Supposely movlhps is faster / better than unpcklpd.
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- Don't forget pshufd is only available with sse2.
llvm-svn: 26956
2006-03-22 19:16:21 +00:00
68ad48bd1a
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
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splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
llvm-svn: 26954
2006-03-22 18:59:22 +00:00
8fdbdf20cd
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
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PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
llvm-svn: 26951
2006-03-22 08:01:21 +00:00
3617caf526
Fix PSHUF* and SHUF* jit code emission problems
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llvm-svn: 26949
2006-03-22 07:10:28 +00:00
d097e67544
Some splat and shuffle support.
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llvm-svn: 26940
2006-03-22 02:53:00 +00:00
d5e905d762
- Use movaps to store 128-bit vector integers.
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- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
1208d9179a
- Remove scalar to vector pseudo ops. They are just wrong.
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- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
e4d1416239
x86 ISD::SCALAR_TO_VECTOR support.
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llvm-svn: 26911
2006-03-21 00:33:35 +00:00
e6448448c2
Move a few things around.
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llvm-svn: 26893
2006-03-20 06:04:52 +00:00
f7c2e3628b
Vector undef's
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llvm-svn: 26870
2006-03-19 09:38:54 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
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V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
4f674921d6
Move some pattern fragments to the right files.
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llvm-svn: 26831
2006-03-17 19:55:52 +00:00
9e252e3bcf
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
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Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
d58478161f
One more round of reorg so sabre doesn't freak out. :-)
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llvm-svn: 26303
2006-02-21 20:00:20 +00:00
6fc1162855
A big more cleaning up.
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llvm-svn: 26302
2006-02-21 19:30:30 +00:00
8711b6bff3
Moving things to their proper places.
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llvm-svn: 26301
2006-02-21 19:26:52 +00:00
6e595b9fd8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
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llvm-svn: 26300
2006-02-21 19:13:53 +00:00
Evan Cheng