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Added SSE cachebility ops 

llvm-svn: 27103
This commit is contained in:
Evan Cheng 2006-03-25 06:03:26 +00:00
parent 1aaa7280cd
commit 79e500ec74
1 changed files with 30 additions and 0 deletions
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30
llvm/lib/Target/X86/X86InstrSSE.td
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@ -891,6 +891,36 @@ def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
// Miscellaneous Instructions
//===----------------------------------------------------------------------===//
// Prefetching loads
def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src),
"prefetcht0 $src", []>, TB,
Requires<[HasSSE1]>;
def PREFETCHT1 : I<0x18, MRM2m, (ops i8mem:$src),
"prefetcht0 $src", []>, TB,
Requires<[HasSSE1]>;
def PREFETCHT2 : I<0x18, MRM3m, (ops i8mem:$src),
"prefetcht0 $src", []>, TB,
Requires<[HasSSE1]>;
def PREFETCHTNTA : I<0x18, MRM0m, (ops i8mem:$src),
"prefetcht0 $src", []>, TB,
Requires<[HasSSE1]>;
// Non-temporal stores
def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
"movntq {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasSSE1]>;
def MOVNTPS : I<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
"movntps {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasSSE1]>;
def MASKMOVQ : I<0xF7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
"maskmovq {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasSSE1]>;
// Store fence
def SFENCE : I<0xAE, MRM7m, (ops),
"sfence", []>, TB, Requires<[HasSSE1]>;
// Load MXCSR register
def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
"ldmxcsr {$src|$src}", []>, TB, Requires<[HasSSE1]>;