e0d58d36b2
comment tweaks
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llvm-svn: 149060
2012-01-26 10:28:58 +00:00
6685c08e5f
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
...
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
llvm-svn: 149057
2012-01-26 09:25:43 +00:00
5f29b0e57b
Fix for the following bug in AVX codegen for double-to-int conversions:
...
. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
. Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
. Consequently, the conversion produces incorrect numbers.
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode.
As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec).
llvm-svn: 149056
2012-01-26 08:51:39 +00:00
86e44bc829
Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
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llvm-svn: 149054
2012-01-26 07:51:55 +00:00
1c0e22f57a
Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.
...
llvm-svn: 149053
2012-01-26 07:31:30 +00:00
b91760eff8
Remove some more patterns by custom lowering intrinsics to target specific nodes.
...
llvm-svn: 149052
2012-01-26 07:18:03 +00:00
34d9a17778
unbreak test/Bitcode/shuffle.ll.
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llvm-svn: 149033
2012-01-26 03:10:45 +00:00
8722fe5a24
simplify by using ShuffleVectorInst::getMaskValue.
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llvm-svn: 149029
2012-01-26 02:54:54 +00:00
cf12970bd0
eliminate the Constant::getVectorElements method. There are better (and
...
more robust) ways to do what it was doing now. Also, add static methods
for decoding a ShuffleVector mask.
llvm-svn: 149028
2012-01-26 02:51:13 +00:00
fa77500d96
Continue improving support for ConstantDataAggregate, and use the
...
new methods recently added to (sometimes greatly!) simplify code.
llvm-svn: 149024
2012-01-26 02:32:04 +00:00
f14a67f5d3
Add a ConstantDataVector::getSplatValue() method, for parity with
...
ConstantVector. Fix some outright bugs in the implementation of
ConstantArray and Constant struct, which would cause us to not make
one big UndefValue when asking for an array/struct with all undef
elements. Enhance Constant::isAllOnesValue to work with
ConstantDataVector.
llvm-svn: 149021
2012-01-26 02:31:22 +00:00
76e1c8c9ae
llvm-config: Add support for CMake build trees in which the build
...
mode does not form part of the path.
llvm-svn: 149010
2012-01-26 01:31:38 +00:00
8326bd8e10
some general cleanup, using new methods and tidying up old code.
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llvm-svn: 149006
2012-01-26 00:42:34 +00:00
3dbad40341
fix pasto in the new (and still unused) ShuffleVectorInst::getShuffleMask method.
...
llvm-svn: 149005
2012-01-26 00:41:50 +00:00
154aabc0c4
add StructType helpers too.
...
llvm-svn: 149000
2012-01-26 00:06:44 +00:00
40a279e1c5
Ok, break down and add some cast<>'ing helper methods to the Type class
...
to reduce the number of cast<>'s we have. This allows someone to use
things like Ty->getVectorNumElements() instead of
cast<VectorType>(Ty)->getNumElements() when you know that a type is a
vector.
It would be a great general cleanup to move the codebase to use these,
I will do so in the code I'm touching.
llvm-svn: 148999
2012-01-26 00:01:10 +00:00
1dcb654311
add some helper methods to ShuffleVectorInst and enhance its
...
"isValidOperands" and "getMaskValue" methods to allow
ConstantDataSequential.
llvm-svn: 148998
2012-01-25 23:49:49 +00:00
4864a81aa3
Improve sub-register def handling in ProcessImplicitDefs.
...
This boils down to using MachineOperand::readsReg() more.
This fixes PR11829 where a use ended up after the first def when
lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs.
llvm-svn: 148996
2012-01-25 23:36:27 +00:00
7722a2d4e3
Properly emit ctors / dtors with priorities into desired sections
...
and let linker handle the rest.
This finally fixes PR5329
llvm-svn: 148990
2012-01-25 22:24:19 +00:00
f1508b78f9
Don't add live ranges for aliases of physregs that are live in to the
...
function. They don't appear to be used, and are inconsistent with handling of
other physreg intervals (i.e. intervals that are not live-in) where ranges are
not inserted for aliases.
llvm-svn: 148986
2012-01-25 22:11:06 +00:00
65e2465550
Tidy up. s/Low Level Virtual Machine/LLVM/.
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LLVM isn't an acronym anymore.
llvm-svn: 148985
2012-01-25 22:00:23 +00:00
19feb5f241
Always break upon finding a vreg operand (in Release as well as +Asserts). Remove assertion which can no longer trigger.
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llvm-svn: 148984
2012-01-25 21:53:23 +00:00
82f76d1275
ARM assemly parsing and validation of IT instruction.
...
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
llvm-svn: 148969
2012-01-25 19:52:01 +00:00
0e496cddf0
Use precomputed BB size instead of BB->size().
...
llvm-svn: 148964
2012-01-25 18:54:13 +00:00
33633a90a0
fix a bug I introduced in r148929, this is not a splat!
...
Thanks to Eli for noticing.
llvm-svn: 148947
2012-01-25 09:56:22 +00:00
3c3feaf40c
Gracefully degrade precision in branch probability numbers.
...
llvm-svn: 148946
2012-01-25 09:43:14 +00:00
70d50ee8fb
Support pointer comparisons against constants, when looking at the inline-cost
...
savings from a pointer argument becoming an alloca. Sometimes callees will even
compare a pointer to null and then branch to an otherwise unreachable block!
Detect these cases and compute the number of saved instructions, instead of
bailing out and reporting no savings.
llvm-svn: 148941
2012-01-25 08:27:40 +00:00
44d69d9c25
Revert a tiny bit of r148553 which extended LLVM's function attributes
...
to 64-bits, and added a new attribute in bit #32 . Specifically, remove
this new attribute from the enum used in the C API. It's not yet clear
what the best approach is for exposing these new attributes in the
C API, and several different proposals are on the table. Until then, we
can simply not expose this bit in the API at all.
Also, I've reverted a somewhat unrelated change in the same revision
which switched from "1 << 31" to "1U << 31" for the top enum. While "1
<< 31" is technically undefined behavior, implementations DTRT here.
However, MS and -pedantic mode warn about non-'int' type enumerator
values. If folks feel strongly about this I can put the 'U' back in, but
it seemed best to wait for the proper solution.
llvm-svn: 148937
2012-01-25 07:40:15 +00:00
ef6a2ea216
Update hasProperty comment.
...
llvm-svn: 148936
2012-01-25 07:38:48 +00:00
6705883ad8
use Constant::getAggregateElement to simplify a bunch of code.
...
llvm-svn: 148934
2012-01-25 06:48:06 +00:00
7834900950
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
...
llvm-svn: 148933
2012-01-25 06:43:11 +00:00
7e683d10a8
constify some methods and add a new Constant::getAggregateElement
...
helper method for the common operation of extracting an element
out of a constant aggregate.
llvm-svn: 148931
2012-01-25 06:16:32 +00:00
47a86bdbe2
use ConstantVector::getSplat in a few places.
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llvm-svn: 148929
2012-01-25 06:02:56 +00:00
ce4f9c5668
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
...
llvm-svn: 148927
2012-01-25 05:37:32 +00:00
e9eed29b5b
reapply r148901 with a crucial fix.
...
"Introduce a new ConstantVector::getSplat constructor function to
simplify a really common case."
llvm-svn: 148924
2012-01-25 05:19:54 +00:00
5bcf070e68
Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
...
llvm-svn: 148922
2012-01-25 04:42:03 +00:00
012f041bce
Mark 64-bit register RA_64 unused too.
...
llvm-svn: 148918
2012-01-25 04:19:22 +00:00
01d3c42f90
Modify MipsFrameLowering::emitPrologue and emitEpilogue.
...
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
instructions which store callee-saved registers have been emitted.
llvm-svn: 148917
2012-01-25 04:12:04 +00:00
d1d4b3efcf
Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to
...
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.
llvm-svn: 148916
2012-01-25 03:55:10 +00:00
3ad5bc019a
Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
...
llvm-svn: 148914
2012-01-25 03:52:09 +00:00
f47efbc07d
-fvisibility-inlines-hidden is a c++ only option.
...
Thanks to Peter Collingbourne for noticing it.
llvm-svn: 148913
2012-01-25 03:39:26 +00:00
6c421ea484
MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.
...
inttypes.h is not supplied in msvc.
llvm-svn: 148912
2012-01-25 03:34:41 +00:00
ff50962534
Fix assert("msg"). Fix unused-variable warnings complaining about VT used only
...
in asserts.
llvm-svn: 148910
2012-01-25 03:20:12 +00:00
96a21dcea3
Target/Mips: Unbreak CMake build.
...
llvm-svn: 148909
2012-01-25 03:15:46 +00:00
86d5fadd57
Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
...
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.
llvm-svn: 148908
2012-01-25 03:01:35 +00:00
939b7a0b7c
Revert r148901 because it crashes llvm tests.
...
Original log:
Introduce a new ConstantVector::getSplat constructor function to
simplify a really common case.
llvm-svn: 148906
2012-01-25 02:42:41 +00:00
9fe7dd872b
Introduce a new ConstantVector::getSplat constructor function to
...
simplify a really common case.
llvm-svn: 148901
2012-01-25 01:53:58 +00:00
ff36fd3de3
Add class MipsAnalyzeImmediate which comes up with an instruction sequence to
...
load an immediate.
llvm-svn: 148900
2012-01-25 01:43:36 +00:00
8a3df5495a
Remove the Type::getNumElements() method, which is only called in 4 places,
...
did something extremely surprising, and shadowed actually useful
implementations that had completely different behavior.
llvm-svn: 148898
2012-01-25 01:32:59 +00:00
9be59599b3
Use the right method to get the # elements in a CDS.
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llvm-svn: 148897
2012-01-25 01:27:20 +00:00
086cbfac7d
NEON VLD4(all lanes) assembly parsing and encoding.
...
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
ccb6d55dae
Tidy up. Rename VLD4DUP patterns for consistency.
...
llvm-svn: 148883
2012-01-24 23:47:07 +00:00
b78403ce48
NEON VLD3(all lanes) assembly parsing and encoding.
...
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
77c4ff2182
Additional methods for SmallString.
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llvm-svn: 148881
2012-01-24 23:43:59 +00:00
1b8e437ab6
Set correct <def,undef> flags when lowering REG_SEQUENCE.
...
A REG_SEQUENCE instruction is lowered into a sequence of partial defs:
%vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0
%vreg7:ssub_1<def> = COPY %vreg2
%vreg7:ssub_2<def> = COPY %vreg2
%vreg7:ssub_3<def> = COPY %vreg2
The first def needs an <undef> flag to indicate it is the beginning of
the live range, while the other defs are read-modify-write. Previously,
we depended on LiveIntervalAnalysis to notice and fix the missing
<def,undef>, but that solution was never robust, it was causing problems
with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE
instructions.
This fixes PR11841.
llvm-svn: 148879
2012-01-24 23:28:42 +00:00
66ef9ad33f
Use the standard MachineFunction::print() after SlotIndexes.
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llvm-svn: 148878
2012-01-24 23:28:38 +00:00
d7970f9e4b
Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
...
which is what N32/64 does.
llvm-svn: 148875
2012-01-24 23:18:43 +00:00
7e6c195c11
Pass CCState by reference.
...
llvm-svn: 148871
2012-01-24 22:07:36 +00:00
77dbd786c8
Pattern for f32 to i64 conversion.
...
llvm-svn: 148869
2012-01-24 22:05:25 +00:00
35bc8f9159
ARM Darwin symbol ref differences w/o subsection-via-symbols.
...
When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.
llvm-svn: 148865
2012-01-24 21:45:25 +00:00
a410ed3ced
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
...
llvm-svn: 148864
2012-01-24 21:43:36 +00:00
9f7ec1538f
64-bit sign extension in register instructions.
...
llvm-svn: 148862
2012-01-24 21:41:09 +00:00
0bba00dc2f
Tidy up. Trailing whitespace.
...
llvm-svn: 148856
2012-01-24 21:06:59 +00:00
88297ef665
Sink assert-only variables into the asserts
...
llvm-svn: 148849
2012-01-24 19:43:30 +00:00
c11d1dd133
[asan] enable asan only for the functions that have Attribute::AddressSafety
...
llvm-svn: 148846
2012-01-24 19:34:43 +00:00
8e2722cdb0
NEON VST4(one lane) assembly parsing and encoding.
...
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
d845d9d9e9
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
...
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
14952a0e32
NEON VLD4(one lane) assembly parsing and encoding.
...
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
5b9deabae8
Fix old doxygen comment.
...
llvm-svn: 148825
2012-01-24 18:09:18 +00:00
60e70e8fcf
Add an (interleave A, B, ...) SetTheory operator.
...
This will interleave the elements from two or more lists.
llvm-svn: 148824
2012-01-24 18:06:05 +00:00
beb3e7e076
Undo an over zealous rename. This bit of the CMake build really is
...
dealing in the host triple, be honest about it and document the decision
to default the target triple to the host triple unless overridden.
llvm-svn: 148822
2012-01-24 18:00:44 +00:00
3cfef8d467
NEON Two-operand assembly aliases for VSRA.
...
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
9ca3a067c8
Remove redundant test file.
...
llvm-svn: 148820
2012-01-24 17:55:32 +00:00
7ae12cc546
NEON Two-operand assembly aliases for VSLI.
...
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
7b6f0f67aa
NEON Two-operand assembly aliases for VSRI.
...
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
1395b67e3b
Tidy up.
...
llvm-svn: 148817
2012-01-24 17:46:54 +00:00
681db34eae
NEON add correct predicates for some asm aliases.
...
llvm-svn: 148815
2012-01-24 17:23:29 +00:00
5c9a69fd1a
Reword comment based on feedback by Duncan Sands.
...
llvm-svn: 148809
2012-01-24 16:18:30 +00:00
a0d01ff567
basic instcombine support for CDS.
...
llvm-svn: 148806
2012-01-24 14:31:22 +00:00
139822fc83
C++, CBE, and TLOF support for ConstantDataSequential
...
llvm-svn: 148805
2012-01-24 14:17:05 +00:00
2068393140
Rearrange argument order of ::get methods so that LLVMContext comes first,
...
add a ConstantDataArray::getString method that corresponds to the (to be
removed) StringRef version of ConstantArray::get, but is dramatically more
efficient.
llvm-svn: 148804
2012-01-24 14:04:40 +00:00
0b0c5d8c4c
ZERO_EXTEND operation is optimized for AVX.
...
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.
llvm-svn: 148803
2012-01-24 13:54:13 +00:00
00245f420a
add more support for ConstantDataSequential
...
llvm-svn: 148802
2012-01-24 13:41:11 +00:00
33a7e2f2a1
An option to selectively enable part of ARM EHABI support.
...
This change adds an new option --arm-enable-ehabi-descriptors that
enables emitting unwinding descriptors. This provides a mode with a
working backtrace() without the (currently broken) exception support.
llvm-svn: 148800
2012-01-24 13:05:33 +00:00
8aefffca4c
Bit pack DIE structures better.
...
16 bits are sufficient to store attributes, tags and forms.
llvm-svn: 148799
2012-01-24 12:08:28 +00:00
df1666e4e6
Fix the testcases for the previous patch.
...
rdar://10278198
llvm-svn: 148795
2012-01-24 10:11:49 +00:00
3e8ccc2000
Remove generation of DW_AT_sibling. Nothing as far as I can tell uses it.
...
Saves about 1.5% on debug info size.
rdar://10278198
llvm-svn: 148794
2012-01-24 09:43:28 +00:00
5d4497bf4a
Add AsmPrinter (aka MCLowering) support for ConstantDataSequential,
...
and clean up some other misc stuff. Unlike ConstantArray, we will
prefer to emit .fill directives for "String" arrays that all have
the same value, since they are denser than emitting a .ascii
llvm-svn: 148793
2012-01-24 09:31:43 +00:00
5dd4d87ce0
Add various "string" methods to ConstantDataSequential, which have the
...
same semantics as ConstantArray's but much more efficient because they
don't have to return std::string's. The ConstantArray methods will
eventually be removed.
llvm-svn: 148792
2012-01-24 09:01:07 +00:00
8e6fde457a
add ::drop_back() and ::drop_front() methods, which are like pop_front/pop_back on a vector, but a) aren't destructive to "this", and b) can take a # elements to drop.
...
llvm-svn: 148791
2012-01-24 08:58:57 +00:00
f7eb543380
teach valuetracking about ConstantDataSequential
...
llvm-svn: 148790
2012-01-24 07:54:10 +00:00
e166a8548f
switch SCEV to use the new ConstantFoldLoadThroughGEPIndices function
...
instead of its own hard coded thing, allowing it to handle
ConstantDataSequential and fixing some obscure bugs (e.g. it would
previously crash on a CAZ of vector type).
llvm-svn: 148788
2012-01-24 05:49:24 +00:00
f488b35826
Split the interesting bits of ConstantFoldLoadThroughGEPConstantExpr
...
out into a new ConstantFoldLoadThroughGEPIndices (more useful) function
and rewrite it to be simpler, more efficient, and to handle the new
ConstantDataSequential type.
Enhance ConstantFoldLoadFromConstPtr to handle ConstantDataSequential.
llvm-svn: 148786
2012-01-24 05:43:50 +00:00
030af79b14
Add some accessor methods to CAZ and UndefValue that help simplify clients.
...
Make some CDS methods public.
llvm-svn: 148785
2012-01-24 05:42:11 +00:00
3cad0c21ed
Use correct register class for am2offset register operands.
...
This pacifies machine verifier
llvm-svn: 148782
2012-01-24 04:58:56 +00:00
c46534a0cd
Preserve <def,undef> flags in CoalesceExtSubRegs.
...
This won't have an effect until EliminateRegSequences() starts setting
the undef flags.
llvm-svn: 148779
2012-01-24 04:44:01 +00:00
e4f3f102c2
implement the ConstantDataSequential accessor methods.
...
No need for 'getOperand' :)
llvm-svn: 148778
2012-01-24 04:43:41 +00:00
0d8e67aebd
Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
...
llvm-svn: 148771
2012-01-24 03:03:17 +00:00
da70eac268
NEON VST4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
ed561fc850
NEON VLD4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
1e946a4f91
Tidy up. Remove some vertical space for readability.
...
llvm-svn: 148761
2012-01-24 00:43:12 +00:00
ed975232bc
Revert r148686 (and r148694, a fix to it) due to a serious layering
...
violation -- MC cannot depend on CodeGen.
Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.
Fixing this is likely going to require some non-trivial refactoring.
llvm-svn: 148759
2012-01-24 00:30:17 +00:00
17bacab475
Fix typo.
...
llvm-svn: 148757
2012-01-24 00:12:39 +00:00
d3d36d9315
NEON VST3(single element from one lane) assembly parsing.
...
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
eba7d3dba9
Fix typo.
...
llvm-svn: 148751
2012-01-23 23:56:33 +00:00
1a74724fc9
NEON VST3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
8abd7b4a35
Changing bitfield enums to unsigned ints.
...
This was suggested by Chandler Carruth on the basis of past experience with
esoteric compilers/quirks relating to signed enums.
llvm-svn: 148746
2012-01-23 23:27:47 +00:00
ac2af3ffab
NEON VLD3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
820417af07
Add missed mayStore flag to STREXD / t2STREXD
...
llvm-svn: 148742
2012-01-23 22:57:52 +00:00
3756b91313
start the implementation of a new ConstantDataVector and ConstantDataArray
...
classes, per PR1324. Not all of their helper functions are implemented,
nothing creates them, and the rest of the compiler doesn't handle them yet.
llvm-svn: 148741
2012-01-23 22:57:10 +00:00
11eeeff24f
Remove extraneous ';'s.
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llvm-svn: 148740
2012-01-23 22:55:02 +00:00
d3303ded75
Remove dead default.
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llvm-svn: 148738
2012-01-23 22:37:11 +00:00
cf893a437e
Intel syntax: Robustify parsing of memory operand's displacement experssion.
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llvm-svn: 148737
2012-01-23 22:35:25 +00:00
3dc3af8ff2
Simplify llvm: 🆑 :Option by using a bit field instead of manual bit packing.
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This still preserves the same total layout.
Previously it looked like:
*** Dumping AST Record Layout
0 | class llvm:🆑 :Option
0 | (Option vtable pointer)
8 | int NumOccurrences
12 | int Flags
16 | unsigned int Position
20 | unsigned int AdditionalVals
24 | class llvm:🆑 :Option * NextRegistered
32 | const char * ArgStr
40 | const char * HelpStr
48 | const char * ValueStr
sizeof=56, dsize=56, align=8
nvsize=56, nvalign=8
Now it looks like:
*** Dumping AST Record Layout
0 | class llvm:🆑 :Option
0 | (Option vtable pointer)
8 | int NumOccurrences
12 | enum NumOccurrencesFlag Occurrences
12 | unsigned int Value
12 | enum OptionHidden HiddenFlag
12 | enum FormattingFlags Formatting
13 | unsigned int Misc
16 | unsigned int Position
20 | unsigned int AdditionalVals
24 | class llvm:🆑 :Option * NextRegistered
32 | const char * ArgStr
40 | const char * HelpStr
48 | const char * ValueStr
sizeof=56, dsize=56, align=8
nvsize=56, nvalign=8
llvm-svn: 148736
2012-01-23 22:22:44 +00:00
a8b444b08b
NEON VLD3 lane-indexed assembly parsing and encoding.
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llvm-svn: 148734
2012-01-23 21:53:26 +00:00
3c47e37387
Add support for .cfi_signal_frame. Fixes pr11762.
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llvm-svn: 148733
2012-01-23 21:51:52 +00:00
599ca4275f
Various public StringMap methods take or return "MapEntryTy", make it public.
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llvm-svn: 148732
2012-01-23 21:42:52 +00:00
2f6377cafe
copyImplicitOps is redundant here - the loop above already copies these ops.
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llvm-svn: 148725
2012-01-23 21:15:01 +00:00
20948fab69
Fix PR11829. PostRA LICM was too aggressive.
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This fixes a typo in r148589.
llvm-svn: 148724
2012-01-23 21:01:15 +00:00
9082353e3b
Simplify debug output.
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llvm-svn: 148723
2012-01-23 21:01:11 +00:00
e660fdd953
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
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llvm-svn: 148721
2012-01-23 20:20:06 +00:00
d28ef9ac46
Simplify some NEON assembly pseudo definitions.
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Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
llvm-svn: 148718
2012-01-23 19:39:08 +00:00
54db64e2e4
Silence warnings in -asserts build
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llvm-svn: 148715
2012-01-23 18:46:04 +00:00
880bc1644b
Intel syntax: Parse segment registers.
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llvm-svn: 148712
2012-01-23 18:31:58 +00:00
c7f9fd4da8
convert CAZ, UndefValue, and CPN to use DenseMap's again, this time without
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using OwningPtr. OwningPtr would barf when the densemap had to reallocate,
which doesn't appear to happen on the regression test suite, but obviously
happens in real life :)
llvm-svn: 148700
2012-01-23 15:20:12 +00:00
de0132a763
revert r148688 too, this isn't safe for DenseMap use. When DenseMap resizes, it will need to copy around arbitrary pointers
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llvm-svn: 148699
2012-01-23 15:10:41 +00:00
962c272f95
revert r148691 and 148693
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llvm-svn: 148698
2012-01-23 15:09:44 +00:00
c94cf8faf6
Implemented AddressSanitizer::getPassName()
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llvm-svn: 148697
2012-01-23 11:22:43 +00:00
28ea8f523b
ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.
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llvm-svn: 148694
2012-01-23 09:14:42 +00:00
4494e1ae25
switch UndefValue and ConstantPointerNull over to DenseMap's for uniquing.
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llvm-svn: 148693
2012-01-23 08:52:32 +00:00
75499f5d04
Fix broken link.
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llvm-svn: 148692
2012-01-23 08:47:21 +00:00
1910c9c3a0
Replace a use of ConstantUniqueMap for CAZ constants with a simple DenseMap.
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Now that the type system rewrite has landed, there is no need for its
complexity and std::map'ness.
llvm-svn: 148691
2012-01-23 08:42:38 +00:00
ff1049146d
allow OwningPtr to be copy constructed if null, which is required to
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make them be a valuetype in a DenseMap.
llvm-svn: 148688
2012-01-23 08:19:57 +00:00
edd1d0acfc
Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
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llvm-svn: 148687
2012-01-23 08:18:28 +00:00
482cdc4ebd
An option to selectively enable parts of ARM EHABI support.
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This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.
llvm-svn: 148686
2012-01-23 07:57:39 +00:00
6b90c5d03e
Update more places to use target specific nodes for vector shifts instead of intrinsics.
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llvm-svn: 148685
2012-01-23 06:46:22 +00:00
5e80db4e4f
Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
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llvm-svn: 148684
2012-01-23 06:16:53 +00:00
624e30894a
Avoid using an invalidated iterator.
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llvm-svn: 148681
2012-01-23 05:07:16 +00:00
abf456e320
The iteration order over a std::set<Module*> depends on the addresses of the
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modules. Avoid that to make the order the linker sees the modules deterministic.
llvm-svn: 148676
2012-01-23 03:41:53 +00:00
20c98df340
Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
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llvm-svn: 148672
2012-01-23 00:06:44 +00:00
c31ceda7d9
Make Value::isDereferenceablePointer() handle unreachable code blocks. (This
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returns false in the event the computation feeding into the pointer is
unreachable, which maybe ought to be true -- but this is at least consistent
with undef->isDereferenceablePointer().) Fixes PR11825!
llvm-svn: 148671
2012-01-23 00:05:17 +00:00
0b7ad76bd0
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
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llvm-svn: 148670
2012-01-22 23:36:02 +00:00
bd4884371b
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
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llvm-svn: 148667
2012-01-22 22:42:16 +00:00
e197d943f3
Use Attributes::None instead of 0 after r148553 change on Attributes from unsigned to their own class.
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llvm-svn: 148665
2012-01-22 20:05:26 +00:00
094626414d
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
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llvm-svn: 148664
2012-01-22 19:15:14 +00:00
0251f20ad1
Add an option to disable buggy copy propagation pass
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llvm-svn: 148662
2012-01-22 14:08:34 +00:00
3119440239
unittests/Support/Casting.cpp: [PR8226] Workaround for MSVC|Debug.
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llvm-svn: 148659
2012-01-22 12:14:35 +00:00
5482b9f535
Add fused multiple+add instructions from VFPv4.
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Patch by Ana Pazos!
llvm-svn: 148658
2012-01-22 12:07:33 +00:00
21c1aa8fd5
Remove trailing spaces
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llvm-svn: 148655
2012-01-22 09:26:00 +00:00
bff72ba77e
Remove trailing spaces
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llvm-svn: 148654
2012-01-22 09:02:48 +00:00
Gabor Greif