15f6ed348f
The predicate index isn't fixed, so scan for it to make sure we get the proper
...
value.
Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.
llvm-svn: 96817
2010-02-22 22:47:46 +00:00
fbc9d8d424
Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
...
the armv6 nightly tests.
llvm-svn: 96691
2010-02-19 18:59:53 +00:00
aa34003f6f
Radar 7636153. In the presence of large call frames, it's not sufficient
...
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.
llvm-svn: 96634
2010-02-19 00:16:24 +00:00
3b065cdb64
Teach MachineFrameInfo to track maximum alignment while stack objects are being
...
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.
llvm-svn: 96069
2010-02-13 01:56:41 +00:00
d0a2f52f8f
As of r79039, we still try to eliminate the frame pointer on leaf functions,
...
even when -disable-fp-elim is specified.
llvm-svn: 95161
2010-02-02 23:56:14 +00:00
f13e5f7323
constify a method argument.
...
llvm-svn: 94612
2010-01-26 23:15:09 +00:00
04770f2aa1
For aligned load/store instructions, it's only required to know whether a
...
function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.
llvm-svn: 93885
2010-01-19 18:31:11 +00:00
b907a467e2
80 column violations
...
llvm-svn: 92876
2010-01-06 23:54:42 +00:00
5fd6feb883
Addressing mode 6 (load/store) instructions can't encode an immediate offset
...
for stack references.
llvm-svn: 92871
2010-01-06 23:45:18 +00:00
6f579c12b1
Use proper move instructions. Make the verifier happy.
...
llvm-svn: 91914
2009-12-22 18:49:55 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
...
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
2c3a6c6589
Factor the stack alignment calculations out into a target independent pass.
...
No functionality change.
llvm-svn: 90336
2009-12-02 19:30:24 +00:00
fd963e11f5
Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values.
...
llvm-svn: 89618
2009-11-22 20:05:32 +00:00
90e9062e96
Generate more correct debug info for frame indices.
...
llvm-svn: 89576
2009-11-22 02:32:29 +00:00
e09e95b35c
Revert 89562. We're being sneakier than I was giving us credit for, and this
...
isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
43fd822249
Darwin requires a frame pointer for all non-leaf functions to support correct
...
backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
56ee15c162
Make the pass class name more explicit.
...
llvm-svn: 88964
2009-11-16 21:13:22 +00:00
544b15cbc3
make pass name a bit more clear
...
llvm-svn: 88961
2009-11-16 21:03:58 +00:00
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
...
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
1fbe054450
Add a bool flag to StackObjects telling whether they reference spill
...
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
llvm-svn: 87022
2009-11-12 20:49:22 +00:00
2524b04d0e
Now that the default is 'enabled,' a separate command line option for ARM is
...
not necessary.
llvm-svn: 86621
2009-11-09 23:11:45 +00:00
1218b804fb
Enable dynamic stack realignment by default.
...
llvm-svn: 86604
2009-11-09 22:32:40 +00:00
55d3480769
Set dynamic stack realignment to real values.
...
llvm-svn: 86602
2009-11-09 22:32:03 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
...
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
a15c3b7124
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
...
llvm-svn: 86425
2009-11-08 00:27:19 +00:00
31569240c6
Grammar.
...
llvm-svn: 86068
2009-11-04 23:20:40 +00:00
5833df9bde
Now that the memory leak from McCat/08-main has been fixed (86056), re-enable
...
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.
llvm-svn: 86064
2009-11-04 23:11:07 +00:00
2c7fd8f1db
If a function has no stack frame at all, dynamic realignment isn't necessary.
...
llvm-svn: 86057
2009-11-04 22:41:51 +00:00
cc58cc1d56
dynamic stack realignment necessitates scanning the floating point callee-
...
saved instructions even if no stack adjustment for those saves is needed.
llvm-svn: 86056
2009-11-04 22:41:00 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
...
llvm-svn: 85871
2009-11-03 05:52:54 +00:00
fbe0256b23
Revert r85049, it is causing PR5367
...
llvm-svn: 85847
2009-11-03 00:24:48 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
8578068302
Dial back the realignment a bit.
...
llvm-svn: 85546
2009-10-30 00:08:40 +00:00
b352d76480
To get more thorough testing from llc-beta nightly runs, do dynamic stack
...
realignment regardless of whether it's strictly necessary.
llvm-svn: 85476
2009-10-29 02:41:21 +00:00
294aea709e
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
...
llvm-svn: 85406
2009-10-28 17:33:28 +00:00
5607d2cb54
Enable virtual register based frame index scavenging by default for ARM & T2.
...
llvm-svn: 85335
2009-10-27 22:52:29 +00:00
c1403a0024
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
...
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
llvm-svn: 85333
2009-10-27 22:45:39 +00:00
2e7dee5f23
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
...
llvm-svn: 85049
2009-10-25 07:53:28 +00:00
f2e74df12e
Missing piece of the ARM frame index post-scavenging conditionalization
...
llvm-svn: 84798
2009-10-21 23:40:56 +00:00
05536f50dc
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
...
for a few bugs.
llvm-svn: 84791
2009-10-21 22:59:24 +00:00
cccf5084a3
Disable by default while debugging
...
llvm-svn: 84669
2009-10-20 20:31:31 +00:00
f3a2b6499e
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
...
llvm-svn: 84664
2009-10-20 20:19:50 +00:00
84f6235b6f
Enable post-pass frame index register scavenging for ARM and Thumb2
...
llvm-svn: 84585
2009-10-20 01:26:58 +00:00
f5f263f1b4
Enable allocation of R3 in Thumb1
...
llvm-svn: 84563
2009-10-19 22:57:03 +00:00
fa14dd430c
Add register-reuse to frame-index register scavenging. When a target uses
...
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
llvm-svn: 83467
2009-10-07 17:12:56 +00:00
2dfb5da6bb
In Thumb1, the register scavenger is not always able to use an emergency
...
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
llvm-svn: 83336
2009-10-05 22:30:23 +00:00
a2fe1a6811
Clarify comment phrasing.
...
llvm-svn: 83148
2009-09-30 15:23:38 +00:00
70ce8a03b1
When checking whether we need to reserve a register for the scavenger,
...
the size of the saved frame pointer needs to be taken into account.
llvm-svn: 83136
2009-09-30 01:43:29 +00:00
fa6847f099
minor cleanup and add clarifying comment
...
llvm-svn: 83117
2009-09-29 23:17:20 +00:00
5264202a38
Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
...
slot for the register scavenger when compiling Thumb1 functions.
llvm-svn: 83023
2009-09-28 22:08:06 +00:00
f7fe0132c9
Add some comments to clarify things that I discovered this week.
...
llvm-svn: 82773
2009-09-25 16:34:46 +00:00
372e9a389b
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
...
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
llvm-svn: 82734
2009-09-24 23:52:18 +00:00
3c21a35908
Fix a typo in an assertion message.
...
llvm-svn: 82284
2009-09-18 21:42:44 +00:00
210d6fef51
Revert array initialization regclass change so that the initialization stays static, not runtime.
...
llvm-svn: 81560
2009-09-11 20:13:17 +00:00
a1072a85d6
Update register class references to use the global constant ARM::*RegisterClass names.
...
llvm-svn: 81556
2009-09-11 19:49:06 +00:00
3033db2448
Fix -Asserts warning, round two.
...
llvm-svn: 80354
2009-08-28 08:08:22 +00:00
d46e3466e7
Fix -Asserts warning.
...
llvm-svn: 80338
2009-08-28 05:47:56 +00:00
7a37b1a2ca
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
...
llvm-svn: 80191
2009-08-27 01:23:50 +00:00
36d747745e
Simplify RegScavenger::FindUnusedReg.
...
- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
llvm-svn: 79369
2009-08-18 21:14:54 +00:00
75c9e535c6
Do not use frame register to reference fixed stack objects if the function is frameless.
...
llvm-svn: 79067
2009-08-15 02:05:35 +00:00
7dae88d2c9
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
...
llvm-svn: 79039
2009-08-14 20:48:13 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
...
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
...
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
f5b73869f2
Use tMOVgpr2gpr instead of t2MOVr.
...
llvm-svn: 78556
2009-08-10 05:49:43 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
5811ab5cf3
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
...
llvm-svn: 77642
2009-07-30 23:29:25 +00:00
ee68a483ec
Give getPointerRegClass() a "kind" value so that targets can
...
support multiple different pointer register classes.
llvm-svn: 77501
2009-07-29 20:31:52 +00:00
d6b4b29706
more simplifications and cleanup. :)
...
llvm-svn: 77350
2009-07-28 18:48:43 +00:00
73a5119675
Code clean up. No functionality changes.
...
llvm-svn: 77301
2009-07-28 06:24:12 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
...
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
18688f431d
Get rid of more dead code.
...
llvm-svn: 77227
2009-07-27 18:38:54 +00:00
239ed4b343
Cosmetic change.
...
llvm-svn: 77222
2009-07-27 18:31:40 +00:00
056c669e93
Get rid of some more getOpcode calls.
...
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
llvm-svn: 77218
2009-07-27 18:20:05 +00:00
c47e109335
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
...
llvm-svn: 77181
2009-07-27 03:14:20 +00:00
8953720f23
Refactor. Get rid of a few more getOpcode() calls.
...
llvm-svn: 77164
2009-07-26 18:55:14 +00:00
ea23c3ba46
80 col violation.
...
llvm-svn: 77041
2009-07-25 01:55:25 +00:00
edb4a70325
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
...
llvm-svn: 77011
2009-07-24 23:12:02 +00:00
6cfbe61361
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
...
llvm-svn: 76925
2009-07-24 00:53:56 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
...
llvm-svn: 76919
2009-07-24 00:16:18 +00:00
6deba28c6f
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
...
llvm-svn: 76883
2009-07-23 17:06:46 +00:00
edda8cbfad
80 col violation.
...
llvm-svn: 76872
2009-07-23 07:58:08 +00:00
2e1d66847c
Get rid one of the getRegisterNumbering. Also add D16 - D31.
...
llvm-svn: 76725
2009-07-22 05:55:18 +00:00
47db941fd3
Get rid of the Pass+Context magic.
...
llvm-svn: 76702
2009-07-22 00:24:57 +00:00
84517443ca
Let callers decide the sub-register index on the def operand of rematerialized instructions.
...
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
llvm-svn: 75900
2009-07-16 09:20:10 +00:00
b6b2530000
Move EVER MORE stuff over to LLVMContext.
...
llvm-svn: 75703
2009-07-14 23:09:55 +00:00
fbcc663cbf
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
...
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
llvm-svn: 75640
2009-07-14 16:55:14 +00:00
160521095b
Fix FP elimination code to work for Thumb-2 addrmode AddrModeT2_so. This fixes SingleSource/Benchmarks/Stanford/Queens (among others).
...
llvm-svn: 75513
2009-07-13 21:43:08 +00:00
56d0659726
assert(0) -> LLVM_UNREACHABLE.
...
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
llvm-svn: 75379
2009-07-11 20:10:48 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
...
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
7bf08beb2e
Handle Thumb-2 addressing modes during FP elimination.
...
llvm-svn: 75158
2009-07-09 18:35:52 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
...
llvm-svn: 75067
2009-07-08 23:10:31 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
...
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
fb8d6d5b58
Implement changes from Chris's feedback.
...
Finish converting lib/Target.
llvm-svn: 75043
2009-07-08 20:53:28 +00:00
03ab0bbb24
Generalize opcode selection in ARMBaseRegisterInfo.
...
llvm-svn: 75036
2009-07-08 20:28:28 +00:00
9ca33e8a9f
Push methods into base class in preparation for sharing.
...
llvm-svn: 75020
2009-07-08 18:31:39 +00:00
6dd2730024
Start converting to new error handling API.
...
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
llvm-svn: 75018
2009-07-08 18:01:40 +00:00
eebf58805c
Start breaking out common base functionality for register info.
...
llvm-svn: 75016
2009-07-08 17:28:55 +00:00
Jim Grosbach