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For aligned load/store instructions, it's only required to know whether a 

function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.

llvm-svn: 93885
This commit is contained in:
Jim Grosbach 2010-01-19 18:31:11 +00:00
parent 18f49ce2d3
commit 04770f2aa1
10 changed files with 21 additions and 87 deletions
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4
llvm/include/llvm/CodeGen/Passes.h
View File

@ -195,10 +195,6 @@ namespace llvm {
/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
FunctionPass *createSjLjEHPass(const TargetLowering *tli);
/// createMaxStackAlignmentCalculatorPass() - Determine the maximum required
/// alignment for a function.
FunctionPass* createMaxStackAlignmentCalculatorPass();
} // End llvm namespace
#endif

70
llvm/lib/CodeGen/MaxStackAlignment.cpp
View File

@ -1,70 +0,0 @@
//===-- MaxStackAlignment.cpp - Compute the required stack alignment -- ---===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This pass looks for vector register usage and aligned local objects to
// calculate the maximum required alignment for a function. This is used by
// targets which support it to determine if dynamic stack realignment is
// necessary.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
using namespace llvm;
namespace {
struct MaximalStackAlignmentCalculator : public MachineFunctionPass {
static char ID;
MaximalStackAlignmentCalculator() : MachineFunctionPass(&ID) {}
virtual bool runOnMachineFunction(MachineFunction &MF) {
MachineFrameInfo *FFI = MF.getFrameInfo();
MachineRegisterInfo &RI = MF.getRegInfo();
// Calculate max stack alignment of all already allocated stack objects.
FFI->calculateMaxStackAlignment();
unsigned MaxAlign = FFI->getMaxAlignment();
// Be over-conservative: scan over all vreg defs and find whether vector
// registers are used. If yes, there is probability that vector registers
// will be spilled and thus the stack needs to be aligned properly.
// FIXME: It would be better to only do this if a spill actually
// happens rather than conseratively aligning the stack regardless.
for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
RegNum < RI.getLastVirtReg(); ++RegNum)
MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
if (FFI->getMaxAlignment() == MaxAlign)
return false;
FFI->setMaxAlignment(MaxAlign);
return true;
}
virtual const char *getPassName() const {
return "Stack Alignment Requirements Auto-Detector";
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
char MaximalStackAlignmentCalculator::ID = 0;
}
FunctionPass*
llvm::createMaxStackAlignmentCalculatorPass() {
return new MaximalStackAlignmentCalculator();
}

4
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -715,7 +715,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
// FIXME: Neon instructions should support predicates
if (Align >= 16
&& (getRegisterInfo().needsStackRealignment(MF))) {
&& (getRegisterInfo().canRealignStack(MF))) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
.addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
.addMemOperand(MMO)
@ -760,7 +760,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
RC == ARM::QPR_VFP2RegisterClass ||
RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
if (Align >= 16
&& (getRegisterInfo().needsStackRealignment(MF))) {
&& (getRegisterInfo().canRealignStack(MF))) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
.addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
.addMemOperand(MMO));

8
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -484,6 +484,14 @@ bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
MFI->isFrameAddressTaken());
}
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
return (RealignStack &&
!AFI->isThumb1OnlyFunction() &&
!MFI->hasVarSizedObjects());
}
bool ARMBaseRegisterInfo::
needsStackRealignment(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();

1
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -96,6 +96,7 @@ public:
bool hasFP(const MachineFunction &MF) const;
bool canRealignStack(const MachineFunction &MF) const;
bool needsStackRealignment(const MachineFunction &MF) const;
bool cannotEliminateFrame(const MachineFunction &MF) const;

4
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -93,10 +93,6 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
if (Subtarget.hasNEON())
PM.add(createNEONPreAllocPass());
// Calculate and set max stack object alignment early, so we can decide
// whether we will need stack realignment (and thus FP).
PM.add(createMaxStackAlignmentCalculatorPass());
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass(true));

6
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -2077,8 +2077,7 @@ void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC) const {
const MachineFunction &MF = *MBB.getParent();
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
@ -2172,8 +2171,7 @@ void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const{
const MachineFunction &MF = *MBB.getParent();
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();

6
llvm/lib/Target/X86/X86RegisterInfo.cpp
View File

@ -438,6 +438,12 @@ bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
(MMI && MMI->callsUnwindInit()));
}
bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return (RealignStack &&
!MFI->hasVarSizedObjects());
}
bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
bool requiresRealignment =

2
llvm/lib/Target/X86/X86RegisterInfo.h
View File

@ -128,6 +128,8 @@ public:
bool hasFP(const MachineFunction &MF) const;
bool canRealignStack(const MachineFunction &MF) const;
bool needsStackRealignment(const MachineFunction &MF) const;
bool hasReservedCallFrame(MachineFunction &MF) const;

3
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@ -157,9 +157,6 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// Calculate and set max stack object alignment early, so we can decide
// whether we will need stack realignment (and thus FP).
PM.add(createMaxStackAlignmentCalculatorPass());
return false; // -print-machineinstr shouldn't print after this.
}