9c609df3c9
Support -print-machineinstrs
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llvm-svn: 12124
2004-03-04 19:22:16 +00:00
82ec4a561b
Asm printer support, based on x86 - only prints mnemonics for now
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llvm-svn: 12113
2004-03-04 06:00:41 +00:00
8ace44fe0d
Double-FP pseudo-registers.
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llvm-svn: 12112
2004-03-04 05:15:03 +00:00
92c95f812d
Subtract instructions; minor cleanups
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llvm-svn: 12111
2004-03-04 04:37:45 +00:00
d2e89190d9
Floating point regs
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llvm-svn: 12110
2004-03-04 04:37:22 +00:00
956fb06a4a
Simple copyConstantToReg support, SETHIi and ORri
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llvm-svn: 12107
2004-03-04 00:56:25 +00:00
165ff998e0
Support add - note, still missing important copyConstantToRegister stuff
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llvm-svn: 12106
2004-03-03 23:03:14 +00:00
427cec1395
TargetCacheInfo has been removed; its only uses were to propagate a constant
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(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.
llvm-svn: 12043
2004-03-01 06:43:29 +00:00
ed01da8f0b
Adjust to change in TII ctor arguments
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llvm-svn: 11987
2004-02-29 06:31:44 +00:00
ca89812db7
These two virtual methods are never called.
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llvm-svn: 11984
2004-02-29 05:59:33 +00:00
e5f08917ae
Implement initial prolog/epilog code insertion methods.
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llvm-svn: 11979
2004-02-29 05:18:30 +00:00
b1862e4d3b
Add an instruction selector capable of selecting 'ret void'
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llvm-svn: 11973
2004-02-29 00:27:00 +00:00
72bb8fcb15
Change this so that LLC actually tries to run the code generator, though it will
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immediately abort due to lack of an instruction selector. :)
llvm-svn: 11963
2004-02-28 20:21:45 +00:00
1a3ee3e961
Finegrainify namespacification
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llvm-svn: 11958
2004-02-28 19:52:49 +00:00
e40fd90b0b
Tab completion is our friend.
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llvm-svn: 11957
2004-02-28 19:45:39 +00:00
0179fb5881
Clean up rules
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llvm-svn: 11956
2004-02-28 19:43:40 +00:00
74598091a1
Bring this directory into "it actually compiles" land
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llvm-svn: 11955
2004-02-28 19:37:18 +00:00
3290952f8b
Fix multiple inclusion problem
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llvm-svn: 11954
2004-02-28 19:31:32 +00:00
1743c4090d
Instructions to call and return from functions.
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llvm-svn: 11858
2004-02-26 00:37:12 +00:00
564654d654
SparcV8 regs are really 32-bit, not 64! Thanks, Chris.
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llvm-svn: 11835
2004-02-25 21:03:02 +00:00
f8dcdcc83b
Clean up the tablegen descriptions for SparcV8.
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llvm-svn: 11834
2004-02-25 21:02:21 +00:00
2122b969f9
Fix the SparcV8 register definitions that were imported from PPC template.
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llvm-svn: 11833
2004-02-25 21:00:05 +00:00
0e3a7ca53e
SparcV8 has different types of instructions, but F1 is only used for CALL.
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llvm-svn: 11832
2004-02-25 20:52:20 +00:00
9a5bd7fca7
SparcV8 skeleton
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llvm-svn: 11828
2004-02-25 19:28:19 +00:00
Brian Gaeke