Bring this directory into "it actually compiles" land

llvm-svn: 11955

llvm/lib/Target/SparcV8/SparcV8Instrs.td

@@ -35,6 +35,17 @@ include "SparcV8Instrs_F3.td"
 // Instructions
 //===----------------------------------------------------------------------===//
 
+// Pseudo instructions.
+def PHI : InstV8 {
+  let Name = "PHI";
+}
+def ADJCALLSTACKDOWN : InstV8 {
+  let Name = "ADJCALLSTACKDOWN";
+}
+def ADJCALLSTACKUP : InstV8 {
+  let Name = "ADJCALLSTACKUP";
+}
+
 // Section B.20: SAVE and RESTORE - p117
 def SAVEr    : F3_1<2, 0b111100, "save">;           // save    r, r, r
 def SAVEi    : F3_2<2, 0b111100, "save">;           // save    r, i, r

llvm/lib/Target/SparcV8/SparcV8Instrs_F2.td

@@ -31,7 +31,7 @@ class F2_1<bits<3> op2Val, string name> : F2 {
   let Inst{29-25} = rd;
 }
 
-class F2_2<bits<4> cond, bits<3> op2Val, string name> : F2 {
+class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
   bits<4>   cond;
   bit       annul = 0;     // currently unused
 

llvm/lib/Target/SparcV8/SparcV8Instrs_F3.td

@@ -47,6 +47,7 @@ class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
   let Inst{12-0} = simm13;
 }
 
+/*
 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfVal, string name> 
   : F3_rs1rs2 {
   bits<5> rs2;
@@ -58,4 +59,4 @@ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfVal, string name>
   let Inst{13-5} = opfVal;
   let Inst{4-0}  = rs2;
 }
-
+*/

llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp

@@ -17,8 +17,8 @@
 using namespace llvm;
 
 SparcV8RegisterInfo::SparcV8RegisterInfo()
-  : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN,
-                           SparcV8::ADJCALLSTACKUP) {}
+  : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
+                           V8::ADJCALLSTACKUP) {}
 
 int SparcV8RegisterInfo::storeRegToStackSlot(
   MachineBasicBlock &MBB,
@@ -80,6 +80,9 @@ void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
 const TargetRegisterClass*
 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
   switch (Ty->getPrimitiveID()) {
+  case Type::FloatTyID:
+  case Type::DoubleTyID:
+    assert(0 && "Floating point registers not supported yet!");
   case Type::LongTyID:
   case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
   default:              assert(0 && "Invalid type to getClass!");
@@ -90,10 +93,7 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
   case Type::UShortTyID:
   case Type::IntTyID:
   case Type::UIntTyID:
-  case Type::PointerTyID: return &GPRCInstance;
-    
-  case Type::FloatTyID:
-  case Type::DoubleTyID: return &FPRCInstance;
+  case Type::PointerTyID: return &IntRegsInstance;
   }
 }