e43ca022bf
In thumb mode, round up stack frame size to multiple of 4 since add/sub
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sp, imm instructions implicitly multiply the offset by 4.
llvm-svn: 33653
2007-01-30 02:57:02 +00:00
c419d983d6
Thumb eliminateFrameIndex fixes.
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llvm-svn: 33652
2007-01-30 02:36:01 +00:00
7fa6964dc2
- In thumb mode, if size of MachineFunction is >= 2048, force LR to be
...
spilled (if it is not already).
- If LR is spilled, use BL to implement far jumps. LR is not used as a GPR
in thumb mode so it can be clobbered if it is properly spilled / restored
in prologue / epilogue.
- If LR is force spilled but no far jump has been emitted, try undo'ing the
spill by:
push lr -> delete
pop pc -> bx lr
llvm-svn: 33650
2007-01-30 01:18:38 +00:00
43e8518d8b
Remember if LR register has been spilled in this function.
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llvm-svn: 33632
2007-01-29 22:22:24 +00:00
add7f164a1
Represent tADDspi and tSUBspi as two-address instructions.
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llvm-svn: 33551
2007-01-26 21:33:19 +00:00
fa824b9f73
I am an idiot.
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llvm-svn: 33509
2007-01-25 23:18:16 +00:00
6730e12ae4
PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.
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llvm-svn: 33460
2007-01-23 09:38:11 +00:00
16e58be1bc
hasFP() is now a virtual method of MRegisterInfo.
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llvm-svn: 33455
2007-01-23 00:57:47 +00:00
e3d8e42e27
Round up stack to multiple of alignment only if it's a leaf function without alloca.
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llvm-svn: 33401
2007-01-20 10:22:33 +00:00
a9af4be5ac
Prologue and epilogue bugs for non-Darwin targets.
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llvm-svn: 33390
2007-01-20 03:24:07 +00:00
aa24f08926
Clean up ARM PEI code.
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llvm-svn: 33389
2007-01-20 02:09:25 +00:00
bf216c364f
isDarwin -> isTargetDarwin
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llvm-svn: 33366
2007-01-19 19:28:01 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
901d9e65f6
Don't add or sub zero to sp.
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llvm-svn: 33142
2007-01-12 20:52:27 +00:00
c4235e5521
Build constants using instructions mov/orr or mvn/eor.
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llvm-svn: 33141
2007-01-12 20:35:49 +00:00
74b46e8c05
Fix naming inconsistency.
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llvm-svn: 32823
2007-01-02 21:33:40 +00:00
3ab9256d19
macros -> Inline functions
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Lauros's patch
llvm-svn: 32656
2006-12-18 11:07:09 +00:00
09e2921d9a
Avoid creating invalid sub/add instructions on the prolog/epilog
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patch by Lauro
llvm-svn: 32577
2006-12-14 13:31:27 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
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llvm-svn: 32333
2006-12-07 22:21:48 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
5f7ab1b964
implement load effective address similar to the alpha backend
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remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
708cb60588
initial implementation of addressing mode 2
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TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
4e825336a0
add support for calling functions when the caller has variable sized objects
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llvm-svn: 31312
2006-10-31 13:03:26 +00:00
a23166d6a4
initial support for frame pointers
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llvm-svn: 31197
2006-10-26 13:31:26 +00:00
feb50708eb
add the immediate to the Offset in eliminateFrameIndex
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llvm-svn: 30998
2006-10-17 14:34:02 +00:00
c31ee94920
add FCPYS and FCPYD
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llvm-svn: 30995
2006-10-17 13:13:23 +00:00
6024ea8383
fix the stack alignment
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llvm-svn: 30766
2006-10-06 14:29:47 +00:00
3130a756ef
add shifts to addressing mode 1
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llvm-svn: 30291
2006-09-13 12:09:43 +00:00
e45a79a9e2
partial implementation of the ARM Addressing Mode 1
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llvm-svn: 30252
2006-09-11 17:25:40 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
c3ed77e1b9
add a "load effective address"
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llvm-svn: 29748
2006-08-17 17:09:40 +00:00
bf8e751488
Declare the callee saved regs
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Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
1c41fc9b06
correctly set LocalAreaOffset of TargetFrameInfo
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llvm-svn: 29589
2006-08-09 17:37:45 +00:00
f5ce475540
fix the spill code
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llvm-svn: 29583
2006-08-09 16:41:12 +00:00
58159b36a3
fix the loading of the link register in emitepilogue
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llvm-svn: 29580
2006-08-09 13:15:47 +00:00
8c41f99e6f
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
39083e7836
initial support for variable number of arguments
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llvm-svn: 29567
2006-08-08 13:02:29 +00:00
976c93a110
implemented sub
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correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
bf3a17cd32
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
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llvm-svn: 29175
2006-07-18 17:00:30 +00:00
185c5c2bdf
add the memri memory operand
...
this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
...
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
f6f5aff038
handle the "mov reg1, reg2" case in isMoveInstr
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llvm-svn: 28945
2006-06-27 21:52:45 +00:00
a88966fd5e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
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fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
b15597b59a
implement movri
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add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
ffdc24b847
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
Evan Cheng