Evan Cheng
0f7cbe8370
Add PredicateOperand to all ARM instructions that have the condition field.
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llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Lauro Ramos Venancio
744350b131
Fix PR1390 in a better way.
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llvm-svn: 36916
2007-05-07 23:15:16 +00:00
Lauro Ramos Venancio
34b2735f20
Fix PR1390.
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Don't spill extra register to align the stack.
llvm-svn: 36814
2007-05-05 23:44:41 +00:00
Lauro Ramos Venancio
83930198dd
Debug support for arm-linux.
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Patch by Raul Herbster.
llvm-svn: 36690
2007-05-03 20:28:35 +00:00
Evan Cheng
5662b21db1
eliminateFrameIndex() change.
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llvm-svn: 36626
2007-05-01 09:13:03 +00:00
Evan Cheng
77c545e6b8
Under normal circumstances, when a frame pointer is not required, we reserve
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argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
llvm-svn: 36607
2007-05-01 00:52:08 +00:00
Lauro Ramos Venancio
99cb63029a
add parenthesis.
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llvm-svn: 36514
2007-04-27 20:10:08 +00:00
Lauro Ramos Venancio
62f65468bc
In Thumb mode, the frame register must be R7.
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llvm-svn: 36512
2007-04-27 17:58:03 +00:00
Evan Cheng
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
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llvm-svn: 36452
2007-04-25 22:13:27 +00:00
Lauro Ramos Venancio
42cd7253b1
Fix a bug in getFrameRegister.
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Reported by Raul Herbster.
llvm-svn: 36262
2007-04-19 14:09:38 +00:00
Anton Korobeynikov
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
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target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
Evan Cheng
39d8b4db92
Fixed a bug that causes codegen of noop like add r0, r0, #0 .
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llvm-svn: 35627
2007-04-03 21:31:21 +00:00
Evan Cheng
61f39d186c
Added MRegisterInfo hook to re-materialize an instruction.
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llvm-svn: 35205
2007-03-20 08:09:38 +00:00
Evan Cheng
9bb01c9f4f
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng
67038e7a8b
Fix one more Thumb eliminateFrameIndex bug.
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llvm-svn: 34990
2007-03-07 00:12:18 +00:00
Evan Cheng
5ed781b0db
Register scavenging is now on by default for ARM.
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llvm-svn: 34987
2007-03-06 22:02:53 +00:00
Evan Cheng
4783ae8ac1
Scavenge a register using the register scavenger when needed.
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llvm-svn: 34966
2007-03-06 10:03:56 +00:00
Dale Johannesen
32bc81341b
eliminate unnecessary reset of SP in epilog on darwin
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llvm-svn: 34824
2007-03-02 01:17:17 +00:00
Evan Cheng
2c0fd3ee4c
Use a spilled free callee-saved register as scratch register.
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llvm-svn: 34785
2007-03-01 08:57:52 +00:00
Evan Cheng
6f059e3e0a
- Track which callee-saved registers are spilled.
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- Some code clean up.
llvm-svn: 34783
2007-03-01 08:26:31 +00:00
Evan Cheng
f6ca943638
Doh. ARM::PC is obvious a reserved register.
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llvm-svn: 34763
2007-02-28 23:12:34 +00:00
Evan Cheng
e8af69632f
Make requiresRegisterScavenging determination on a per MachineFunction basis.
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llvm-svn: 34711
2007-02-28 00:59:19 +00:00
Evan Cheng
30508919c8
Start making use of RegScavenger.
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llvm-svn: 34708
2007-02-28 00:21:58 +00:00
Evan Cheng
71a7271b8b
Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info.
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llvm-svn: 34692
2007-02-27 21:12:35 +00:00
Lauro Ramos Venancio
0eb70ebbe5
bugfix: SP wasn't updated for varargs when frame pointer was eliminated.
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llvm-svn: 34537
2007-02-23 21:53:48 +00:00
Evan Cheng
15af662314
Add option to turn on register scavenger; By default, spills kills the register being stored.
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llvm-svn: 34514
2007-02-23 01:09:11 +00:00
Jim Laskey
3796abea0f
Support to provide exception and selector registers.
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llvm-svn: 34482
2007-02-21 22:54:50 +00:00
Evan Cheng
f7ed82da10
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
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llvm-svn: 34428
2007-02-19 21:49:54 +00:00
Reid Spencer
da81bf4d3e
For PR1207:
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Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
Evan Cheng
9865be6d40
Added getReservedRegs().
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llvm-svn: 34376
2007-02-17 11:06:00 +00:00
Evan Cheng
2ff4c973b1
isLowRegister() expects input is a physical register.
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llvm-svn: 34013
2007-02-07 21:44:33 +00:00
Evan Cheng
cca9b1d768
Rename.
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llvm-svn: 34011
2007-02-07 21:24:09 +00:00
Evan Cheng
ec4c67f0a7
If sp offset will be materialized in a register. Clear the offset field of str / ldr.
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llvm-svn: 34010
2007-02-07 21:19:58 +00:00
Evan Cheng
62aef236de
Get rid of references to iostream.
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llvm-svn: 34009
2007-02-07 21:18:32 +00:00
Evan Cheng
78c5a9422d
In thumb mode, R3 is reserved, but it can be live in to the function. If
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that is the case, whenever we use it as a scratch register, save it to R12
first and then restore it after the use.
This is a temporary and truly horrible workaround!
llvm-svn: 33999
2007-02-07 09:17:36 +00:00
Evan Cheng
b5519b5361
- If fp (r7) is used to reference stack objects, use [r, r] address mode.
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- If there is a dynamic alloca, in the epilogue, restore the value of sp
using r7 - offset.
- Other bug fixes.
llvm-svn: 33997
2007-02-07 08:37:31 +00:00
Evan Cheng
12cf8ddaea
eliminateFrameIndex() is even more complicated if frame ptr is used instead of SP when there are dynamic alloca's.
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llvm-svn: 33975
2007-02-07 02:44:23 +00:00
Evan Cheng
ec13f826a2
Spill / restore should avoid modifying the condition register.
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llvm-svn: 33971
2007-02-07 00:06:56 +00:00
Evan Cheng
ea3308aef0
foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers.
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llvm-svn: 33958
2007-02-06 06:13:29 +00:00
Evan Cheng
2fc792f86b
eliminateFrameIndex() bug when frame pointer is used as base register.
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llvm-svn: 33945
2007-02-06 00:23:31 +00:00
Lauro Ramos Venancio
b739f7d337
bugfix: SP isn't resetted when function has FP and there is no spills.
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llvm-svn: 33800
2007-02-02 23:08:40 +00:00
Evan Cheng
f089c99f1d
Another thumb large stack offset codegen bug.
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llvm-svn: 33795
2007-02-02 21:08:39 +00:00
Evan Cheng
fda6550545
Ugh. Only meant to do this in thumb mode.
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llvm-svn: 33780
2007-02-02 08:58:48 +00:00
Evan Cheng
e724492566
Also set alignment of stack-based structs to 4 in thumb mode.
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llvm-svn: 33741
2007-02-01 02:18:36 +00:00
Evan Cheng
e7e966de5e
Special epilogue for vararg functions. We cannot do a pop to pc because
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there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
pop {r4, r5, r6, r7}
pop {r3}
add sp, #3 * 4
bx r3
llvm-svn: 33739
2007-02-01 01:49:46 +00:00
Evan Cheng
b0ff625a31
Don't want to add FramePtr to callee save spill list twice.
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llvm-svn: 33727
2007-01-31 23:17:29 +00:00
Evan Cheng
6f1c20a8e6
Darwin ABI requires FP to point to stack slot of prev FP.
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llvm-svn: 33724
2007-01-31 22:25:33 +00:00
Evan Cheng
ffe1d9f7fa
Update comment.
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llvm-svn: 33721
2007-01-31 22:06:44 +00:00
Lauro Ramos Venancio
7ae4f5599e
ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.
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llvm-svn: 33703
2007-01-31 13:12:46 +00:00
Evan Cheng
dd7a688bb8
During PEI, if the immediate value of sp + offset is too large (i.e. something
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that would require > 3 instructions to materialize), load the immediate from a
constpool entry.
llvm-svn: 33667
2007-01-30 23:01:46 +00:00