e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
afa1cb6da3
Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.
...
llvm-svn: 37173
2007-05-17 18:45:50 +00:00
632c3f01ed
Added missing patterns for UNPCKH* and PUNPCKH*.
...
llvm-svn: 37172
2007-05-17 18:44:37 +00:00
dade607f19
This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't
...
cause other regressions.
llvm-svn: 37160
2007-05-17 17:13:13 +00:00
1ad4618715
Revert patch for PR1427. It breaks almost all vector tests.
...
llvm-svn: 37159
2007-05-17 07:50:14 +00:00
13f4bf5c5e
add support for 128-bit integer add/sub
...
llvm-svn: 37154
2007-05-17 06:35:11 +00:00
6a5a46322f
Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll
...
llvm-svn: 37141
2007-05-17 03:29:42 +00:00
888653cdba
implement the missing maskmovq mmx intrinsic that akor hit.
...
llvm-svn: 37100
2007-05-16 06:08:17 +00:00
c8798d085c
fix subtle bugs in inline asm operand selection
...
llvm-svn: 37065
2007-05-15 01:28:08 +00:00
13da17843c
More DWARF-related things cleanup:
...
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.
llvm-svn: 37015
2007-05-12 22:36:25 +00:00
623c738fe9
add some notes
...
llvm-svn: 36965
2007-05-10 00:08:04 +00:00
f985c492e1
3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.
...
llvm-svn: 36860
2007-05-06 07:56:19 +00:00
4060c7ac63
Reference correct header
...
llvm-svn: 36834
2007-05-06 04:00:55 +00:00
be8f99ecbb
move CodeGen/X86/overlap-add.ll here.
...
llvm-svn: 36799
2007-05-05 22:10:24 +00:00
4db0090339
Emit sections/directives in the proper order. This fixes PR1376. Also,
...
some small cleanup was made.
llvm-svn: 36780
2007-05-05 09:04:50 +00:00
e6182267d7
Add an "implies" field to features. This indicates that, if the current
...
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.
llvm-svn: 36756
2007-05-04 20:38:40 +00:00
83df45a959
Fix two classes of bugs:
...
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
2. the matcher didn't correctly reject and accept some global addresses.
the right predicate is GVRequiresExtraLoad, not "relomodel = pic".
llvm-svn: 36670
2007-05-03 16:52:29 +00:00
e27e6e6fa8
Sets the section names for fixed-size constants and use the mergeable
...
flag for ELF on x86 so that duplicate constants can be eliminated by
the linker. This matches what GCC does with its -fmerge-constants
option, which is enabled at most -O levels.
llvm-svn: 36666
2007-05-03 16:38:57 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
b5ce7c5466
Non-algorithmic change. Moved definitions around into separate sections
...
for SSE1, SSE2, SSE3, and SSSE3.
llvm-svn: 36656
2007-05-02 23:11:52 +00:00
ba3b7ee030
Update.
...
llvm-svn: 36653
2007-05-02 21:42:20 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
f1dcf69fc3
Emit correct register move information in eh frames for X86. This allows Shootout-C++/except to pass on x86/linux
...
with non-llvm-compiled (e.g. "native") unwind runtime.
llvm-svn: 36647
2007-05-02 19:53:33 +00:00
073ad20459
Emit correct DWARF reg # for RA (return address) register
...
llvm-svn: 36646
2007-05-02 08:46:03 +00:00
b538f67b1a
Fix couple of bugs connected with eh info:
...
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.
llvm-svn: 36633
2007-05-01 22:23:12 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
76c8c95466
Use correct PC symbol
...
llvm-svn: 36628
2007-05-01 10:19:31 +00:00
2ac2197a0f
Adjust correct EH-related sections
...
llvm-svn: 36627
2007-05-01 10:16:06 +00:00
5662b21db1
eliminateFrameIndex() change.
...
llvm-svn: 36626
2007-05-01 09:13:03 +00:00
39f3cffbe3
Implement protected visibility. This partly implements PR1363. Linker
...
should be taught to deal with protected symbols.
llvm-svn: 36565
2007-04-29 18:35:00 +00:00
a30eabdd6e
Fix PR1339 and CodeGen/X86/dollar-name.ll
...
llvm-svn: 36495
2007-04-26 21:07:05 +00:00
c8264ca457
Have MMX registers clobbered in x86-64 too.
...
llvm-svn: 36494
2007-04-26 21:06:48 +00:00
ce6e6db704
Fix for PR1348. If stack inc / dec amount is > 32-bits, issue a series of add / sub instructions.
...
llvm-svn: 36456
2007-04-26 01:09:28 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
157d7ee7e5
Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
...
clobbered by a call.
llvm-svn: 36448
2007-04-25 21:31:48 +00:00
d20cd6658a
do the multiplication as signed, so that 2*-2 == -4 instead of 4294967292
...
when promoted to 64-bits
llvm-svn: 36442
2007-04-25 17:23:53 +00:00
a97b694c82
Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part
...
will follow.
llvm-svn: 36435
2007-04-25 14:27:10 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
...
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
b975bebec1
support for >4G stack frames
...
llvm-svn: 36425
2007-04-25 04:30:24 +00:00
1ef35a2721
support >4G stack frames
...
llvm-svn: 36423
2007-04-25 04:25:10 +00:00
a784d875be
Update.
...
llvm-svn: 36407
2007-04-24 21:20:03 +00:00
b3b6c35beb
Add the PADDQ to the list.
...
llvm-svn: 36406
2007-04-24 21:19:14 +00:00
5c7f25632e
Add the final MMX instructions. Correct a few wrong patterns.
...
llvm-svn: 36405
2007-04-24 21:18:37 +00:00
e2324ca17d
Remove some invalid instructions from this check.
...
llvm-svn: 36404
2007-04-24 21:17:46 +00:00
591eab8844
Support for the special case of a vector with the canonical form:
...
vector_shuffle v1, v2, <2, 6, 3, 7>
I.e.
vector_shuffle v, undef, <2, 2, 3, 3>
MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.
llvm-svn: 36403
2007-04-24 21:16:55 +00:00
6db679a49a
X86 TLS: optimize the implementation of "local exec" model.
...
llvm-svn: 36359
2007-04-23 01:28:10 +00:00
efb8077ddd
X86 TLS: fix and optimize the implementation of "initial exec" model.
...
llvm-svn: 36355
2007-04-22 22:50:52 +00:00
4e91908f17
X86 TLS: Implement review feedback.
...
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
5959f42498
Comment out usage of write() for now.
...
llvm-svn: 36287
2007-04-20 22:40:10 +00:00
2518889872
Implement "general dynamic", "initial exec" and "local exec" TLS models for
...
X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
06a164c6bc
Specify sub-register relations. e.g. RAX: [EAX], EAX: [AX], AX: [AL,AH].
...
llvm-svn: 36279
2007-04-20 21:15:21 +00:00
6c673ac01c
Make Microsoft assembler and linker happy.
...
llvm-svn: 36265
2007-04-20 00:33:54 +00:00
29845cd40d
Fix the spelling of the prefetchnta instruction.
...
llvm-svn: 36256
2007-04-18 14:09:14 +00:00
9b91d98a30
Add comment
...
llvm-svn: 36213
2007-04-17 19:34:00 +00:00
ff0598de75
rename X86FunctionInfo to X86MachineFunctionInfo to match the header file
...
it is defined in.
llvm-svn: 36196
2007-04-17 17:21:52 +00:00
8b7aab009e
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
...
Also, fixed static case in presence of eax livin. This fixes PR331
PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195
2007-04-17 09:20:00 +00:00
62a8cbe594
SSE4 is apparently public now.
...
llvm-svn: 36185
2007-04-17 00:02:37 +00:00
6f3a548ff4
In the event that some really old non-Intel or -AMD CPU is encountered...
...
llvm-svn: 36177
2007-04-16 21:59:44 +00:00
da17029218
Before assuming that the original code didn't work for Athlon64, the person who
...
replaced it with a FIXME should have determined what did work. Then he would have
realized that the code was in fact correct, and would have avoided breaking it.
llvm-svn: 36173
2007-04-16 21:48:58 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
e275463e2f
add a note
...
llvm-svn: 36028
2007-04-14 23:06:09 +00:00
2805bce656
Fix mmx paddq, add support for the 'y' register class, though it isn't tested.
...
llvm-svn: 35940
2007-04-12 04:14:49 +00:00
a5fcd24746
Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
...
llvm-svn: 35926
2007-04-11 22:29:46 +00:00
a6aa0319f1
done
...
llvm-svn: 35884
2007-04-11 05:34:00 +00:00
f099841573
Add support for our first SSSE3 instruction "pmulhrsw".
...
llvm-svn: 35869
2007-04-10 22:10:25 +00:00
d4a9b92a13
new micro optzn
...
llvm-svn: 35867
2007-04-10 21:14:01 +00:00
808ac93f68
remove some dead hooks
...
llvm-svn: 35845
2007-04-09 23:31:19 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
7451e4d6a1
move a bunch of register constraints from being handled by
...
getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint. This allows us to let the llvm register allocator
allocate, which gives us better code. For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:
_run_init_process:
subl $4, %esp
movl %ebx, (%esp)
xorl %ebx, %ebx
movl $11, %eax
movl %ebx, %ecx
movl %ebx, %edx
# InlineAsm Start
push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
Now we get:
_run_init_process:
xorl %ecx, %ecx
movl $11, %eax
movl %ecx, %edx
# InlineAsm Start
push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
llvm-svn: 35804
2007-04-09 05:49:22 +00:00
2b6b4eb471
implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values
...
used with x constraints.
llvm-svn: 35803
2007-04-09 05:31:48 +00:00
590ed5e5b7
implement CodeGen/X86/inline-asm-x-scalar.ll
...
llvm-svn: 35799
2007-04-09 05:11:28 +00:00
ac5b650a54
Adding more MMX instructions.
...
llvm-svn: 35638
2007-04-03 23:48:32 +00:00
f79fb5cad0
make a new missing features section
...
llvm-svn: 35637
2007-04-03 23:41:34 +00:00
2640b4a4ab
Updated
...
llvm-svn: 35634
2007-04-03 23:37:20 +00:00
652c7b2d73
Changed to new MMX_ recipes.
...
llvm-svn: 35617
2007-04-03 06:18:31 +00:00
e7b2a864f2
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
...
llvm-svn: 35616
2007-04-03 06:00:37 +00:00
59a6fa7af6
fix breakage from last night, simplify code.
...
llvm-svn: 35560
2007-04-01 20:49:36 +00:00
a8cc1ebae1
Consistency with native compilers
...
llvm-svn: 35532
2007-03-31 13:11:52 +00:00
b72fcddd23
Fix comment.
...
llvm-svn: 35531
2007-03-31 09:36:12 +00:00
afddb2c6f8
Match GCC's MMX calling convention.
...
llvm-svn: 35523
2007-03-31 01:03:53 +00:00
1eb94d973a
implement the new addressing mode description hook.
...
llvm-svn: 35521
2007-03-30 23:15:24 +00:00
2fbcbc16b4
Add MMX calling conventions.
...
llvm-svn: 35489
2007-03-30 00:35:22 +00:00
4ad38abd40
Made this into a bug report: PR1286
...
llvm-svn: 35439
2007-03-28 19:07:34 +00:00
0ad22563b8
Oops :)
...
llvm-svn: 35438
2007-03-28 18:38:33 +00:00
7522c9d8e1
Don't allow MatchAddress recurse too much. This trims exponential
...
behaviour in some cases.
llvm-svn: 35437
2007-03-28 18:36:33 +00:00
2ba38c8711
add a note
...
llvm-svn: 35435
2007-03-28 18:17:19 +00:00
bcd38852f2
Compile CodeGen/X86/lea-3.ll:test2 to:
...
_test3:
leaq (,%rdi,4), %rax
orq %rdi, %rax
ret
instead of:
_test2:
movq %rdi, %rax
shlq $2, %rax
orq %rdi, %rax
ret
llvm-svn: 35434
2007-03-28 18:12:31 +00:00
a6527d6a61
Dan pointed out that this is done, remove it!
...
llvm-svn: 35430
2007-03-28 17:26:52 +00:00
2338e21b2b
Remove cruft I put in there...
...
llvm-svn: 35394
2007-03-28 01:02:54 +00:00
c56e4920d2
Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the
...
system assembler not groking legal instructions like "leal (,%esi,8), %ecx".
llvm-svn: 35393
2007-03-28 00:58:40 +00:00
ad2db4a4cf
Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic.
...
llvm-svn: 35392
2007-03-28 00:57:11 +00:00
999c77f89c
Add the "unpack low packed data" instructions. This should be the last of
...
the MMX instructions that are needed...
llvm-svn: 35389
2007-03-27 21:20:36 +00:00
6dff51ae65
Fix so that pandn is emitted instead of an xor/and combo. Add integer
...
comparison operators.
llvm-svn: 35385
2007-03-27 20:22:40 +00:00
158f6092a2
Promote to v1i64 type...
...
llvm-svn: 35353
2007-03-26 08:03:33 +00:00
48a24419bf
Updated.
...
llvm-svn: 35352
2007-03-26 07:55:58 +00:00
98d2104c6f
Add support for the v1i64 type. This makes better code for this:
...
#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
llvm-svn: 35351
2007-03-26 07:53:08 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
927f30da08
Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers.
...
llvm-svn: 35320
2007-03-25 02:01:03 +00:00
03a643aa69
enforce the proper range for the i386 N constraint.
...
llvm-svn: 35319
2007-03-25 01:57:35 +00:00
c8ddca703d
Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
...
llvm-svn: 35318
2007-03-25 01:44:57 +00:00
Evan Cheng