67e2e22e97
Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan.
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llvm-svn: 39974
2007-07-17 18:03:34 +00:00
9ae2eb43d8
Use push / pop for prologues and epilogues.
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llvm-svn: 39967
2007-07-17 07:59:08 +00:00
383a324735
Long live the exception handling!
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This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
bdc69595d9
another missed SSE optimization
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llvm-svn: 39772
2007-07-12 06:31:38 +00:00
68471d263f
Fix fp_constant_op failure.
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llvm-svn: 38514
2007-07-10 21:53:30 +00:00
23f631d87c
fix 80 columnn violations, increasing the world's
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pedantic satisfaction level.
llvm-svn: 38512
2007-07-10 20:53:41 +00:00
f51bd666d9
add a note
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llvm-svn: 38507
2007-07-10 20:03:50 +00:00
57111e7a60
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
...
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
llvm-svn: 38478
2007-07-10 00:05:58 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
...
zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
d771e05121
isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
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llvm-svn: 37960
2007-07-06 23:22:03 +00:00
b567e3ffb0
Add the byval attribute
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llvm-svn: 37940
2007-07-06 10:57:03 +00:00
de9c825859
Proper flag __alloca call
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llvm-svn: 37923
2007-07-05 20:36:08 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
...
their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
8590f920c7
Support generation of GR64 to MMX code in the JIT.
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llvm-svn: 37866
2007-07-04 01:29:22 +00:00
3053244b27
Allow a GR64 to be moved into an MMX register via the "movd" instruction.
...
Still need to have JIT generate this code.
llvm-svn: 37863
2007-07-04 00:19:54 +00:00
c2a6089b8b
Some spacing fixes. Cosmetic.
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llvm-svn: 37853
2007-07-03 17:07:33 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
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model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
f9ae1c6001
Vector results may be returned in XMM0 and XMM1, not just XMM0. With
...
the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.
llvm-svn: 37844
2007-07-02 16:21:53 +00:00
2660cef6d7
Convert .cvsignore files
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llvm-svn: 37801
2007-06-29 16:35:07 +00:00
444d3ca53d
No vector fneg.
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llvm-svn: 37786
2007-06-29 00:18:15 +00:00
3bd318e298
Type of vector extract / insert index operand should be iPTR.
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llvm-svn: 37784
2007-06-29 00:01:20 +00:00
1cbdcac409
Remove a redundant newline in the asm output for ELF .rodata sections.
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llvm-svn: 37756
2007-06-27 15:09:47 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
...
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
2e84e3f7b7
Make minor adjustments to whitespace and comments to reduce differences
...
between SSE1 instructions and their respective SSE2 analogues.
llvm-svn: 37718
2007-06-25 15:44:19 +00:00
33209bd6b8
Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet.
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llvm-svn: 37717
2007-06-25 15:19:03 +00:00
e33c4b739b
Say AT&T instead of Intel in the comments for AT&T support.
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llvm-svn: 37716
2007-06-25 15:11:25 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
485531ea9b
Quote complex names for Darwin X86 and ARM.
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llvm-svn: 37700
2007-06-22 00:54:56 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
944200be45
If a function is vararg, never pass inreg arguments in registers. Thanks to
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Anton for half of this patch.
llvm-svn: 37641
2007-06-19 00:13:10 +00:00
cea02ffd05
Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.
...
llvm-svn: 37636
2007-06-19 00:02:56 +00:00
c98815ba32
Define the pushq instruction for x86-64.
...
llvm-svn: 37625
2007-06-18 14:12:56 +00:00
094a4e813a
Revert patch. It regresses:
...
define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
llvm-svn: 37617
2007-06-16 23:57:15 +00:00
cd9673e565
Fix a failure to bit_convert from integer GPR to MMX register.
...
llvm-svn: 37611
2007-06-16 06:17:31 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
...
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
616627b002
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
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llvm-svn: 37578
2007-06-14 22:03:45 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
...
implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
3a8e2a8b2f
Eliminate some redundant newlines in asm output.
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llvm-svn: 37574
2007-06-14 15:00:27 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
...
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
75372ad603
fix x86-64 mmx calling convention for real, which passes in integer gprs.
...
llvm-svn: 37534
2007-06-09 05:08:10 +00:00
a4a49e37ab
fix mmx handling bug
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llvm-svn: 37533
2007-06-09 05:01:50 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
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llvm-svn: 37528
2007-06-08 21:59:56 +00:00
59ca6a846f
Misuse of hasExternalLinkage(), should be checking isDeclaration().
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llvm-svn: 37419
2007-06-04 18:54:57 +00:00
703e0f8608
Add explicit qualification for namespace MVT members.
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llvm-svn: 37320
2007-05-24 14:33:05 +00:00
3fb7fdfded
We only need to specify the most-implied feature for an architecture.
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llvm-svn: 37275
2007-05-22 05:15:37 +00:00
fc94eb66d2
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
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llvm-svn: 37266
2007-05-21 18:44:17 +00:00
7ea2df6e2a
add a note
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llvm-svn: 37239
2007-05-18 20:18:14 +00:00
eefa83e67b
Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.
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llvm-svn: 37234
2007-05-18 18:44:07 +00:00
Evan Cheng