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235 Commits

Author SHA1 Message Date
Eric Christopher e796253217 A slight reworking of the custom patterns for x86-64 tpoff codegen and 
correct the testcase for valid assembly.

Needs more tests.

llvm-svn: 107860
 2010-07-08 07:36:46 +00:00
Bruno Cardoso Lopes 3df55b2d6f Use only one multiclass to pinsrq instructions 
llvm-svn: 107750
 2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes fd6c808154 Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes 
llvm-svn: 107749
 2010-07-07 01:33:38 +00:00
Eric Christopher fa6ce139a9 Add a couple more quick comments. 
llvm-svn: 106717
 2010-06-24 02:07:57 +00:00
Eric Christopher 5fed9b7c6c Update according to feedback. 
llvm-svn: 106677
 2010-06-23 20:49:35 +00:00
Eric Christopher 3d6e2c6335 Update uses, defs, and comments for darwin tls patterns. 
llvm-svn: 106621
 2010-06-23 08:01:49 +00:00
Eric Christopher bf572c7cea Add some codegen patterns for x86_64-linux-gnu tls codegen matching. 
Based on a patch by Patrick Marlier!

llvm-svn: 106433
 2010-06-21 18:21:27 +00:00
Eric Christopher 3577c1b811 Remove isTwoAddress from 64-bit files. 
llvm-svn: 106356
 2010-06-18 23:51:21 +00:00
Eric Christopher 67d25f91c5 Some assorted isTwoAddress -> Constraints cleanup. 
llvm-svn: 106273
 2010-06-18 02:41:19 +00:00
Eric Christopher 89d103a8ce Ensure that mov and not lea are used to stick the address into 
the register.  While we're at it, make sure it's in the right one.

llvm-svn: 105645
 2010-06-08 22:04:25 +00:00
Eric Christopher b0e1a458ce Add first pass at darwin tls compiler support. 
llvm-svn: 105381
 2010-06-03 04:07:48 +00:00
Daniel Dunbar c0b69020cd AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected 
to be matched.

llvm-svn: 104757
 2010-05-26 22:21:28 +00:00
Kevin Enderby c798965e63 The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required 
for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621
 2010-05-25 18:16:58 +00:00
Jakob Stoklund Olesen 9340ea59e1 Rename X86 subregister indices to something shorter. 
Use the tablegen-produced enums.

llvm-svn: 104493
 2010-05-24 14:48:17 +00:00
Daniel Dunbar b52fcd6304 MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: 
addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

llvm-svn: 104453
 2010-05-22 21:02:33 +00:00
Daniel Dunbar baf2eea6f4 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
llvm-svn: 104275
 2010-05-20 20:36:29 +00:00
Daniel Dunbar 61655aa2bb X86: Model i64i32imm properly, as a subclass of all immediates. 
llvm-svn: 104272
 2010-05-20 20:20:39 +00:00
Daniel Dunbar 6d4c66dc1d X86: Fix immediate type of FOO64i32 operations. 
llvm-svn: 104271
 2010-05-20 20:20:35 +00:00
Dan Gohman 29790edb93 Fix assembly parsing and encoding of the pushf and popf family of 
instructions.

llvm-svn: 104231
 2010-05-20 16:16:00 +00:00
Dan Gohman 5238275478 Set neverHasSideEffects on 64-bit pushf and popf, for consistency with 
16-bit and 32-bit pushf and popf.

llvm-svn: 104228
 2010-05-20 15:42:55 +00:00
Dan Gohman 02d9947e60 Add mayLoad and mayStore flags to instructions which missed them. 
llvm-svn: 103776
 2010-05-14 16:34:55 +00:00
Chris Lattner 348dc9b15a fix rdar://7947167 - llvm-mc doesn't match movsq 
llvm-svn: 103199
 2010-05-06 21:48:14 +00:00
Sean Callanan e7e1cf9fbd Eliminated the classification of control registers into %ecr_ 
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196
 2010-05-06 20:59:00 +00:00
Kevin Enderby 8f0037097f Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode 
changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.

llvm-svn: 102991
 2010-05-04 00:42:46 +00:00
Kevin Enderby e3a1726034 Fixed the encoding of two of the X86 movq instuctions. The Move quadword from 
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.

llvm-svn: 102952
 2010-05-03 21:03:31 +00:00
Dan Gohman 57bb73c80b Remove the -disable-16bit command-line option, which is now obsolete. 
llvm-svn: 102730
 2010-04-30 18:30:26 +00:00
Evan Cheng 050df1b8de Enable i16 to i32 promotion by default. 
llvm-svn: 102493
 2010-04-28 08:30:49 +00:00
Evan Cheng 347e3b8f15 Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). 
llvm-svn: 102485
 2010-04-28 01:18:01 +00:00
Chris Lattner ec5fe65838 fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest 
nodes all have an EFLAGS result when made by isel lowering.

llvm-svn: 99736
 2010-03-28 05:07:17 +00:00
Chris Lattner 07943af506 eliminate the last of the parallel's! 
llvm-svn: 99700
 2010-03-27 02:47:14 +00:00
Chris Lattner cca83a7aa4 remove 64-bit or_is_add parallels. 
llvm-svn: 99360
 2010-03-24 00:16:52 +00:00
Chris Lattner 8352941b34 remove the patterns that I commented out in r98930, Dan verified 
that they are dead.

llvm-svn: 99000
 2010-03-19 21:43:36 +00:00
Daniel Dunbar c532697372 MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher. 
llvm-svn: 98972
 2010-03-19 18:07:48 +00:00
Chris Lattner 607795f917 comment out a bunch of parallel store patterns that apparently 
can't match or just have no testcases.  Will remove after 
confirmation from dan that they really are dead.

llvm-svn: 98930
 2010-03-19 04:14:21 +00:00
Daniel Dunbar c9deca20e8 X86: Fix encoding for TEST64rr. 
llvm-svn: 98919
 2010-03-19 01:15:03 +00:00
Chris Lattner 83facb0812 Now that tblgen can handle matching implicit defs of instructions 
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.

llvm-svn: 98903
 2010-03-19 00:01:11 +00:00
Chris Lattner eaceb9fd39 callq is pcrelative 
llvm-svn: 98835
 2010-03-18 17:52:22 +00:00
Chris Lattner cf910439ee fix the same bug on the x86-64 side of the fence. 
llvm-svn: 98616
 2010-03-16 06:39:08 +00:00
Evan Cheng 6a9e10905b Fix jit encoding bugs. 
llvm-svn: 98510
 2010-03-14 19:28:34 +00:00
Evan Cheng d703df67ce Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. 
llvm-svn: 98465
 2010-03-14 03:48:46 +00:00
Daniel Dunbar f3530bdd8a X86_64: Fix encoding for the rest of the 64i32 instructions too. 
llvm-svn: 98458
 2010-03-13 22:57:53 +00:00
Daniel Dunbar d324a7c990 X86: Fix ADD64i32 encoding. 
llvm-svn: 98457
 2010-03-13 22:49:39 +00:00
Daniel Dunbar 906a432031 MC/X86_64: Fix matching of leaq. 
llvm-svn: 98444
 2010-03-13 19:31:44 +00:00
Daniel Dunbar e60c883bf4 MC/X86_64: Fix matching of callq. 
llvm-svn: 98443
 2010-03-13 19:31:38 +00:00
Chris Lattner a6d842fac0 Correct immediate sizes. 
llvm-svn: 97957
 2010-03-08 18:55:15 +00:00
Chris Lattner 3fcbbd8673 factor the 'sign extended from 8 bit' patterns better so 
that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.

llvm-svn: 97629
 2010-03-03 01:45:01 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Chris Lattner a2075d44ad fix an incorrect (overly conservative) predicate. 
llvm-svn: 97316
 2010-02-27 08:18:55 +00:00
Chris Lattner d17089231a remove a bunch of dead named arguments in input patterns, 
though some look dubious afaict, these are all ok.

llvm-svn: 96899
 2010-02-23 06:54:29 +00:00
Chris Lattner 48370e14e7 fix a type mismatch in this pattern, where we were using an i64 imm in a 
place where an i32 imm was required, the old isel just got lucky.

This fixes CodeGen/X86/x86-64-and-mask.ll

llvm-svn: 96894
 2010-02-23 06:09:57 +00:00