Chris Lattner
parent
81c03447fc
commit
07943af506
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@ -508,8 +508,8 @@ let isCommutable = 1 in
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def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86add_flag GR64:$src1, GR64:$src2))]>;
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// These are alternate spellings for use by the disassembler, we mark them as
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// code gen only to ensure they aren't matched by the assembler.
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@ -523,21 +523,21 @@ let isCodeGenOnly = 1 in {
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def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
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(ins GR64:$src1, i64i8imm:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
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def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
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(ins GR64:$src1, i64i32imm:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
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} // isConvertibleToThreeAddress
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// Register-Memory Addition
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def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86add_flag GR64:$src1, (load addr:$src2)))]>;
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} // isTwoAddress
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@ -604,8 +604,8 @@ let isTwoAddress = 1 in {
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def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"sub{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86sub_flag GR64:$src1, GR64:$src2))]>;
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def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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@ -615,20 +615,20 @@ def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
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def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"sub{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86sub_flag GR64:$src1, (load addr:$src2)))]>;
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// Register-Integer Subtraction
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def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
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(ins GR64:$src1, i64i8imm:$src2),
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"sub{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
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def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
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(ins GR64:$src1, i64i32imm:$src2),
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"sub{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
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} // isTwoAddress
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def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i32imm:$src),
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@ -716,15 +716,15 @@ let isCommutable = 1 in
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def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"imul{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
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(implicit EFLAGS)]>, TB;
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
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// Register-Memory Signed Integer Multiplication
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def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"imul{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
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(implicit EFLAGS)]>, TB;
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
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} // isTwoAddress
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// Suprisingly enough, these are not two address instructions!
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@ -733,27 +733,27 @@ def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
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def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
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(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
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def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
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// Memory-Integer Signed Integer Multiplication
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def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
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(outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, (mul (load addr:$src1),
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i64immSExt8:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i64immSExt8:$src2))]>;
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def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
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(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, (mul (load addr:$src1),
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i64immSExt32:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i64immSExt32:$src2))]>;
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} // Defs = [EFLAGS]
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// Unsigned division / remainder
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@ -787,16 +787,14 @@ def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
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let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
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def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
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[(set GR64:$dst, (add GR64:$src, 1)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src))]>;
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def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
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[(store (add (loadi64 addr:$dst), 1), addr:$dst),
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(implicit EFLAGS)]>;
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let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
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def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
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[(set GR64:$dst, (add GR64:$src, -1)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src))]>;
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def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
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[(store (add (loadi64 addr:$dst), -1), addr:$dst),
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(implicit EFLAGS)]>;
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@ -806,23 +804,19 @@ let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
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// Can transform into LEA.
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def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
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"inc{w}\t$dst",
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[(set GR16:$dst, (add GR16:$src, 1)),
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(implicit EFLAGS)]>,
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[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
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OpSize, Requires<[In64BitMode]>;
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def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
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"inc{l}\t$dst",
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[(set GR32:$dst, (add GR32:$src, 1)),
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(implicit EFLAGS)]>,
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[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
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Requires<[In64BitMode]>;
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def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
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"dec{w}\t$dst",
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[(set GR16:$dst, (add GR16:$src, -1)),
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(implicit EFLAGS)]>,
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[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
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OpSize, Requires<[In64BitMode]>;
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def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
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"dec{l}\t$dst",
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[(set GR32:$dst, (add GR32:$src, -1)),
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(implicit EFLAGS)]>,
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[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
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Requires<[In64BitMode]>;
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} // isConvertibleToThreeAddress
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@ -1092,26 +1086,26 @@ let isCommutable = 1 in
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def AND64rr : RI<0x21, MRMDestReg,
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(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"and{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86and_flag GR64:$src1, GR64:$src2))]>;
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def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"and{q}\t{$src2, $dst|$dst, $src2}", []>;
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def AND64rm : RI<0x23, MRMSrcMem,
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(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
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"and{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86and_flag GR64:$src1, (load addr:$src2)))]>;
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def AND64ri8 : RIi8<0x83, MRM4r,
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(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
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"and{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
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def AND64ri32 : RIi32<0x81, MRM4r,
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"and{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86and_flag GR64:$src1, i64immSExt32:$src2))]>;
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} // isTwoAddress
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def AND64mr : RI<0x21, MRMDestMem,
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@ -1135,26 +1129,26 @@ let isCommutable = 1 in
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def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"or{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86or_flag GR64:$src1, GR64:$src2))]>;
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def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"or{q}\t{$src2, $dst|$dst, $src2}", []>;
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def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"or{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86or_flag GR64:$src1, (load addr:$src2)))]>;
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def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
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(ins GR64:$src1, i64i8imm:$src2),
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"or{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
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def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
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(ins GR64:$src1, i64i32imm:$src2),
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"or{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
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} // isTwoAddress
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def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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@ -1178,26 +1172,26 @@ let isCommutable = 1 in
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def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"xor{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86xor_flag GR64:$src1, GR64:$src2))]>;
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def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"xor{q}\t{$src2, $dst|$dst, $src2}", []>;
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def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"xor{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86xor_flag GR64:$src1, (load addr:$src2)))]>;
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def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
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(ins GR64:$src1, i64i8imm:$src2),
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"xor{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
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def XOR64ri32 : RIi32<0x81, MRM6r,
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"xor{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
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(implicit EFLAGS)]>;
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[(set GR64:$dst, EFLAGS,
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(X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
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} // isTwoAddress
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def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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@ -2212,136 +2206,76 @@ def : Pat<(subc GR64:$src1, imm:$src2),
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// EFLAGS-defining Patterns
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//===----------------------------------------------------------------------===//
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// Register-Register Addition with EFLAGS result
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def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
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(implicit EFLAGS)),
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// addition
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def : Pat<(add GR64:$src1, GR64:$src2),
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(ADD64rr GR64:$src1, GR64:$src2)>;
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// Register-Integer Addition with EFLAGS result
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def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
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(implicit EFLAGS)),
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def : Pat<(add GR64:$src1, i64immSExt8:$src2),
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(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
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def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
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(implicit EFLAGS)),
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def : Pat<(add GR64:$src1, i64immSExt32:$src2),
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(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
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// Register-Memory Addition with EFLAGS result
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def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
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(implicit EFLAGS)),
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def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
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(ADD64rm GR64:$src1, addr:$src2)>;
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// Register-Register Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
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(implicit EFLAGS)),
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// subtraction
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def : Pat<(sub GR64:$src1, GR64:$src2),
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(SUB64rr GR64:$src1, GR64:$src2)>;
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// Register-Memory Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
|
||||
(SUB64rm GR64:$src1, addr:$src2)>;
|
||||
|
||||
// Register-Integer Subtraction with EFLAGS result
|
||||
def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
|
||||
(SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
|
||||
(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
// Register-Register Signed Integer Multiplication with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
|
||||
(implicit EFLAGS)),
|
||||
// Multiply
|
||||
def : Pat<(mul GR64:$src1, GR64:$src2),
|
||||
(IMUL64rr GR64:$src1, GR64:$src2)>;
|
||||
|
||||
// Register-Memory Signed Integer Multiplication with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
|
||||
(IMUL64rm GR64:$src1, addr:$src2)>;
|
||||
|
||||
// Register-Integer Signed Integer Multiplication with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
|
||||
(IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
|
||||
(IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
// Memory-Integer Signed Integer Multiplication with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
|
||||
(IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
|
||||
(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
// INC and DEC with EFLAGS result. Note that these do not set CF.
|
||||
def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
|
||||
(INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
|
||||
def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
|
||||
(DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
|
||||
// inc/dec
|
||||
def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
|
||||
def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
|
||||
def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
|
||||
def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
|
||||
def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
|
||||
def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
|
||||
|
||||
def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
|
||||
(INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
|
||||
def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
|
||||
(DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
|
||||
|
||||
def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
|
||||
(INC64r GR64:$src)>;
|
||||
def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
|
||||
(DEC64r GR64:$src)>;
|
||||
|
||||
// Register-Register Logical Or with EFLAGS result
|
||||
def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
|
||||
(implicit EFLAGS)),
|
||||
// or
|
||||
def : Pat<(or GR64:$src1, GR64:$src2),
|
||||
(OR64rr GR64:$src1, GR64:$src2)>;
|
||||
|
||||
// Register-Integer Logical Or with EFLAGS result
|
||||
def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(or GR64:$src1, i64immSExt8:$src2),
|
||||
(OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(or GR64:$src1, i64immSExt32:$src2),
|
||||
(OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
// Register-Memory Logical Or with EFLAGS result
|
||||
def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
|
||||
(OR64rm GR64:$src1, addr:$src2)>;
|
||||
|
||||
// Register-Register Logical XOr with EFLAGS result
|
||||
def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
|
||||
(implicit EFLAGS)),
|
||||
// xor
|
||||
def : Pat<(xor GR64:$src1, GR64:$src2),
|
||||
(XOR64rr GR64:$src1, GR64:$src2)>;
|
||||
|
||||
// Register-Integer Logical XOr with EFLAGS result
|
||||
def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
|
||||
(XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
|
||||
(XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
// Register-Memory Logical XOr with EFLAGS result
|
||||
def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
|
||||
(XOR64rm GR64:$src1, addr:$src2)>;
|
||||
|
||||
// Register-Register Logical And with EFLAGS result
|
||||
def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
|
||||
(implicit EFLAGS)),
|
||||
// and
|
||||
def : Pat<(and GR64:$src1, GR64:$src2),
|
||||
(AND64rr GR64:$src1, GR64:$src2)>;
|
||||
|
||||
// Register-Integer Logical And with EFLAGS result
|
||||
def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(and GR64:$src1, i64immSExt8:$src2),
|
||||
(AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(and GR64:$src1, i64immSExt32:$src2),
|
||||
(AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
// Register-Memory Logical And with EFLAGS result
|
||||
def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
|
||||
(AND64rm GR64:$src1, addr:$src2)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -4822,13 +4822,8 @@ def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
|
|||
|
||||
// Optimize multiply by 2 with EFLAGS result.
|
||||
let AddedComplexity = 2 in {
|
||||
def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16rr GR16:$src1, GR16:$src1)>;
|
||||
|
||||
def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32rr GR32:$src1, GR32:$src1)>;
|
||||
def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
|
||||
def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
|
||||
}
|
||||
|
||||
// Patterns for nodes that do not produce flags, for instructions that do.
|
||||
|
|
|
|||
Loading…
Reference in New Issue