Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
This commit is contained in:
Bill Wendling
parent
b41d838d28
commit
fb706bc52b
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@ -135,6 +135,10 @@ namespace llvm {
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/// for the Sparc.
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FunctionPass *getRegisterAllocator(TargetMachine &T);
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/// createMachineLICMPass - This pass performs LICM on machine instructions.
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///
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FunctionPass *createMachineLICMPass();
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} // End llvm namespace
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#endif
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@ -66,7 +66,9 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
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// Print the instruction selected machine code...
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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PM.add(createMachineLICMPass());
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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@ -92,7 +94,7 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (!Fast)
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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// Fold redundant debug labels.
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PM.add(createDebugLabelFoldingPass());
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@ -175,7 +177,9 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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// Print the instruction selected machine code...
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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PM.add(createMachineLICMPass());
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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@ -204,7 +208,7 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (!Fast)
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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if (addPreEmitPass(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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@ -0,0 +1,336 @@
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//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bill Wendling and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs loop invariant code motion on machine instructions. We
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// attempt to remove as much code from the body of a loop as possible.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-licm"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include <map>
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using namespace llvm;
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namespace {
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// Hidden options to help debugging
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cl::opt<bool>
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PerformLICM("machine-licm",
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cl::init(false), cl::Hidden);
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}
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namespace {
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class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
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// Various analyses that we use...
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MachineLoopInfo *LI; // Current MachineLoopInfo
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MachineDominatorTree *DT; // Machine dominator tree for the current Loop
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const TargetInstrInfo *TII;
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// State that is updated as we process loops
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bool Changed; // True if a loop is changed.
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MachineLoop *CurLoop; // The current loop we are working on.
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// Map the def of a virtual register to the machine instruction.
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std::map<unsigned, const MachineInstr*> VRegDefs;
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public:
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static char ID; // Pass identification, replacement for typeid
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MachineLICM() : MachineFunctionPass((intptr_t)&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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/// FIXME: Loop preheaders?
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///
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<MachineDominatorTree>();
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}
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private:
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/// GatherAllLoops - Get all loops in depth first order.
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///
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void GatherAllLoops(MachineLoop *L, SmallVectorImpl<MachineLoop*> &Loops) {
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const std::vector<MachineLoop*> &SubLoops = L->getSubLoops();
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for (MachineLoop::iterator
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I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I)
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GatherAllLoops(*I, Loops);
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Loops.push_back(L);
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}
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/// MapVirtualRegisterDefs - Create a map of which machine instruction
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/// defines a virtual register.
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///
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void MapVirtualRegisterDefs(const MachineFunction &MF);
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/// isInSubLoop - A little predicate that returns true if the specified
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/// basic block is in a subloop of the current one, not the current one
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/// itself.
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///
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bool isInSubLoop(MachineBasicBlock *BB) {
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assert(CurLoop->contains(BB) && "Only valid if BB is IN the loop");
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for (MachineLoop::iterator
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I = CurLoop->begin(), E = CurLoop->end(); I != E; ++I)
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if ((*I)->contains(BB))
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return true; // A subloop actually contains this block!
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return false;
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}
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/// CanHoistInst - Checks that this instructions is one that can be hoisted
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/// out of the loop. I.e., it has no side effects, isn't a control flow
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/// instr, etc.
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///
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bool CanHoistInst(MachineInstr &I) const {
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const TargetInstrDescriptor *TID = I.getInstrDescriptor();
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MachineOpCode Opcode = TID->Opcode;
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return TII->isTriviallyReMaterializable(&I) &&
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// FIXME: Below necessary?
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!(TII->isReturn(Opcode) ||
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TII->isTerminatorInstr(Opcode) ||
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TII->isBranch(Opcode) ||
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TII->isIndirectBranch(Opcode) ||
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TII->isBarrier(Opcode) ||
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TII->isCall(Opcode) ||
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TII->isLoad(Opcode) || // TODO: Do loads and stores.
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TII->isStore(Opcode));
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}
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/// isLoopInvariantInst - Returns true if the instruction is loop
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/// invariant. I.e., all virtual register operands are defined outside of
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/// the loop, physical registers aren't accessed (explicitly or implicitly),
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/// and the instruction is hoistable.
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///
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bool isLoopInvariantInst(MachineInstr &I);
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/// FindPredecessors - Get all of the predecessors of the loop that are not
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/// back-edges.
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///
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void FindPredecessors(std::vector<MachineBasicBlock*> &Preds){
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const MachineBasicBlock *Header = CurLoop->getHeader();
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for (MachineBasicBlock::const_pred_iterator
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I = Header->pred_begin(), E = Header->pred_end(); I != E; ++I)
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if (!CurLoop->contains(*I))
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Preds.push_back(*I);
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}
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/// MoveInstToBlock - Moves the machine instruction to the bottom of the
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/// predecessor basic block (but before the terminator instructions).
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///
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void MoveInstToBlock(MachineBasicBlock *MBB, MachineInstr *MI) {
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MachineBasicBlock::iterator Iter = MBB->getFirstTerminator();
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MBB->insert(Iter, MI);
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}
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/// HoistRegion - Walk the specified region of the CFG (defined by all
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/// blocks dominated by the specified block, and that are in the current
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/// loop) in depth first order w.r.t the DominatorTree. This allows us to
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/// visit definitions before uses, allowing us to hoist a loop body in one
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/// pass without iteration.
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///
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void HoistRegion(MachineDomTreeNode *N);
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/// Hoist - When an instruction is found to only use loop invariant operands
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/// that is safe to hoist, this instruction is called to do the dirty work.
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///
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bool Hoist(MachineInstr &MI);
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};
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char MachineLICM::ID = 0;
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RegisterPass<MachineLICM> X("machine-licm",
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"Machine Loop Invariant Code Motion");
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} // end anonymous namespace
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FunctionPass *llvm::createMachineLICMPass() { return new MachineLICM(); }
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/// Hoist expressions out of the specified loop. Note, alias info for inner loop
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/// is not preserved so it is not a good idea to run LICM multiple times on one
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/// loop.
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///
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bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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if (!PerformLICM) return false; // For debugging.
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Changed = false;
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TII = MF.getTarget().getInstrInfo();
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// Get our Loop information...
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LI = &getAnalysis<MachineLoopInfo>();
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DT = &getAnalysis<MachineDominatorTree>();
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for (MachineLoopInfo::iterator
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I = LI->begin(), E = LI->end(); I != E; ++I) {
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MachineLoop *L = *I;
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CurLoop = L;
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// Visit all of the instructions of the loop. We want to visit the subloops
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// first, though, so that we can hoist their invariants first into their
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// containing loop before we process that loop.
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SmallVector<MachineLoop*, 16> Loops;
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GatherAllLoops(L, Loops);
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for (SmallVector<MachineLoop*, 8>::iterator
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II = Loops.begin(), IE = Loops.end(); II != IE; ++II) {
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L = *II;
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// Traverse the body of the loop in depth first order on the dominator
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// tree so that we are guaranteed to see definitions before we see uses.
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HoistRegion(DT->getNode(L->getHeader()));
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}
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}
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return Changed;
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}
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/// MapVirtualRegisterDefs - Create a map of which machine instruction defines a
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/// virtual register.
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///
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void MachineLICM::MapVirtualRegisterDefs(const MachineFunction &MF) {
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for (MachineFunction::const_iterator
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I = MF.begin(), E = MF.end(); I != E; ++I) {
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const MachineBasicBlock &MBB = *I;
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for (MachineBasicBlock::const_iterator
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II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
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const MachineInstr &MI = *II;
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if (MI.getNumOperands() > 0) {
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const MachineOperand &MO = MI.getOperand(0);
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if (MO.isRegister() && MO.isDef() &&
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MRegisterInfo::isVirtualRegister(MO.getReg()))
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VRegDefs[MO.getReg()] = &MI;
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}
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}
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}
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}
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/// HoistRegion - Walk the specified region of the CFG (defined by all blocks
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/// dominated by the specified block, and that are in the current loop) in depth
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/// first order w.r.t the DominatorTree. This allows us to visit definitions
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/// before uses, allowing us to hoist a loop body in one pass without iteration.
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///
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void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
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assert(N != 0 && "Null dominator tree node?");
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MachineBasicBlock *BB = N->getBlock();
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// If this subregion is not in the top level loop at all, exit.
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if (!CurLoop->contains(BB)) return;
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// Only need to process the contents of this block if it is not part of a
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// subloop (which would already have been processed).
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if (!isInSubLoop(BB))
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for (MachineBasicBlock::iterator
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I = BB->begin(), E = BB->end(); I != E; ) {
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MachineInstr &MI = *I++;
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// Try hoisting the instruction out of the loop. We can only do this if
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// all of the operands of the instruction are loop invariant and if it is
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// safe to hoist the instruction.
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if (Hoist(MI))
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// Hoisting was successful! Remove bothersome instruction now.
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MI.getParent()->remove(&MI);
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}
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const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
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for (unsigned I = 0, E = Children.size(); I != E; ++I)
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HoistRegion(Children[I]);
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}
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/// isLoopInvariantInst - Returns true if the instruction is loop
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/// invariant. I.e., all virtual register operands are defined outside of the
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/// loop, physical registers aren't accessed (explicitly or implicitly), and the
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/// instruction is hoistable.
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///
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bool MachineLICM::isLoopInvariantInst(MachineInstr &I) {
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const TargetInstrDescriptor *TID = I.getInstrDescriptor();
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// Don't hoist if this instruction implicitly reads physical registers or
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// doesn't take any operands.
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if (TID->ImplicitUses || !I.getNumOperands()) return false;
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if (!CanHoistInst(I)) return false;
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// The instruction is loop invariant if all of its operands are loop-invariant
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for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = I.getOperand(i);
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if (!MO.isRegister() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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// Don't hoist instructions that access physical registers.
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if (!MRegisterInfo::isVirtualRegister(Reg))
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return false;
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assert(VRegDefs[Reg] && "Machine instr not mapped for this vreg?!");
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// If the loop contains the definition of an operand, then the instruction
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// isn't loop invariant.
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if (CurLoop->contains(VRegDefs[Reg]->getParent()))
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return false;
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}
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// If we got this far, the instruction is loop invariant!
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return true;
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}
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/// Hoist - When an instruction is found to only use loop invariant operands
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/// that is safe to hoist, this instruction is called to do the dirty work.
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///
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bool MachineLICM::Hoist(MachineInstr &MI) {
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if (!isLoopInvariantInst(MI)) return false;
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std::vector<MachineBasicBlock*> Preds;
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// Non-back-edge predecessors.
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FindPredecessors(Preds);
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if (Preds.empty()) return false;
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// Check that the predecessors are qualified to take the hoisted
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// instruction. I.e., there is only one edge from each predecessor, and it's
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// to the loop header.
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for (std::vector<MachineBasicBlock*>::iterator
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I = Preds.begin(), E = Preds.end(); I != E; ++I) {
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MachineBasicBlock *MBB = *I;
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// FIXME: We are assuming at first that the basic blocks coming into this
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// loop have only one successor each. This isn't the case in general because
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// we haven't broken critical edges or added preheaders.
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if (MBB->succ_size() != 1) return false;
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assert(*MBB->succ_begin() == CurLoop->getHeader() &&
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"The predecessor doesn't feed directly into the loop header!");
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}
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// Now move the instructions to the predecessors.
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for (std::vector<MachineBasicBlock*>::iterator
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I = Preds.begin(), E = Preds.end(); I != E; ++I)
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MoveInstToBlock(*I, MI.clone());
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Changed = true;
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return true;
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}
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@ -684,12 +684,15 @@ def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
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def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
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"subfic $rD, $rA, $imm", IntGeneral,
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[(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
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def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
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"li $rD, $imm", IntGeneral,
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[(set GPRC:$rD, immSExt16:$imm)]>;
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def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
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"lis $rD, $imm", IntGeneral,
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[(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
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let isReMaterializable = 1 in {
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def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
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"li $rD, $imm", IntGeneral,
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[(set GPRC:$rD, immSExt16:$imm)]>;
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def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
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"lis $rD, $imm", IntGeneral,
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[(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
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}
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||||
}
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let PPC970_Unit = 1 in { // FXU Operations.
|
||||
|
|
|
|||
Loading…
Reference in New Issue