From fb706bc52bd61c4c426ff3d7a9cb2b16560b5c5a Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Fri, 7 Dec 2007 21:42:31 +0000 Subject: [PATCH] Initial commit of the machine code LICM pass. It successfully hoists this: _foo: li r2, 0 LBB1_1: ; bb li r5, 0 stw r5, 0(r3) addi r2, r2, 1 addi r3, r3, 4 cmplw cr0, r2, r4 bne cr0, LBB1_1 ; bb LBB1_2: ; return blr to: _foo: li r2, 0 li r5, 0 LBB1_1: ; bb stw r5, 0(r3) addi r2, r2, 1 addi r3, r3, 4 cmplw cr0, r2, r4 bne cr0, LBB1_1 ; bb LBB1_2: ; return blr ZOMG!! :-) Moar to come... llvm-svn: 44687 --- llvm/include/llvm/CodeGen/Passes.h | 4 + llvm/lib/CodeGen/LLVMTargetMachine.cpp | 12 +- llvm/lib/CodeGen/MachineLICM.cpp | 336 ++++++++++++++++++++++++ llvm/lib/Target/PowerPC/PPCInstrInfo.td | 15 +- 4 files changed, 357 insertions(+), 10 deletions(-) create mode 100644 llvm/lib/CodeGen/MachineLICM.cpp diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index 5e93525ab479..f0aa5082fe24 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -135,6 +135,10 @@ namespace llvm { /// for the Sparc. FunctionPass *getRegisterAllocator(TargetMachine &T); + /// createMachineLICMPass - This pass performs LICM on machine instructions. + /// + FunctionPass *createMachineLICMPass(); + } // End llvm namespace #endif diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index 526c5255fe3a..7776d67b2adb 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -66,7 +66,9 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, // Print the instruction selected machine code... if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - + + PM.add(createMachineLICMPass()); + // Perform register allocation to convert to a concrete x86 representation PM.add(createRegisterAllocator()); @@ -92,7 +94,7 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, // Branch folding must be run after regalloc and prolog/epilog insertion. if (!Fast) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); - + // Fold redundant debug labels. PM.add(createDebugLabelFoldingPass()); @@ -175,7 +177,9 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, // Print the instruction selected machine code... if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - + + PM.add(createMachineLICMPass()); + // Perform register allocation to convert to a concrete x86 representation PM.add(createRegisterAllocator()); @@ -204,7 +208,7 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, // Branch folding must be run after regalloc and prolog/epilog insertion. if (!Fast) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); - + if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp new file mode 100644 index 000000000000..443b88c74983 --- /dev/null +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -0,0 +1,336 @@ +//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by Bill Wendling and is distributed under the +// University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass performs loop invariant code motion on machine instructions. We +// attempt to remove as much code from the body of a loop as possible. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "machine-licm" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Support/CFG.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetMachine.h" +#include + +using namespace llvm; + +namespace { + // Hidden options to help debugging + cl::opt + PerformLICM("machine-licm", + cl::init(false), cl::Hidden); +} + +namespace { + class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass { + // Various analyses that we use... + MachineLoopInfo *LI; // Current MachineLoopInfo + MachineDominatorTree *DT; // Machine dominator tree for the current Loop + + const TargetInstrInfo *TII; + + // State that is updated as we process loops + bool Changed; // True if a loop is changed. + MachineLoop *CurLoop; // The current loop we are working on. + + // Map the def of a virtual register to the machine instruction. + std::map VRegDefs; + public: + static char ID; // Pass identification, replacement for typeid + MachineLICM() : MachineFunctionPass((intptr_t)&ID) {} + + virtual bool runOnMachineFunction(MachineFunction &MF); + + /// FIXME: Loop preheaders? + /// + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesCFG(); + AU.addRequired(); + AU.addRequired(); + } + private: + /// GatherAllLoops - Get all loops in depth first order. + /// + void GatherAllLoops(MachineLoop *L, SmallVectorImpl &Loops) { + const std::vector &SubLoops = L->getSubLoops(); + + for (MachineLoop::iterator + I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I) + GatherAllLoops(*I, Loops); + + Loops.push_back(L); + } + + /// MapVirtualRegisterDefs - Create a map of which machine instruction + /// defines a virtual register. + /// + void MapVirtualRegisterDefs(const MachineFunction &MF); + + /// isInSubLoop - A little predicate that returns true if the specified + /// basic block is in a subloop of the current one, not the current one + /// itself. + /// + bool isInSubLoop(MachineBasicBlock *BB) { + assert(CurLoop->contains(BB) && "Only valid if BB is IN the loop"); + + for (MachineLoop::iterator + I = CurLoop->begin(), E = CurLoop->end(); I != E; ++I) + if ((*I)->contains(BB)) + return true; // A subloop actually contains this block! + + return false; + } + + /// CanHoistInst - Checks that this instructions is one that can be hoisted + /// out of the loop. I.e., it has no side effects, isn't a control flow + /// instr, etc. + /// + bool CanHoistInst(MachineInstr &I) const { + const TargetInstrDescriptor *TID = I.getInstrDescriptor(); + MachineOpCode Opcode = TID->Opcode; + + return TII->isTriviallyReMaterializable(&I) && + // FIXME: Below necessary? + !(TII->isReturn(Opcode) || + TII->isTerminatorInstr(Opcode) || + TII->isBranch(Opcode) || + TII->isIndirectBranch(Opcode) || + TII->isBarrier(Opcode) || + TII->isCall(Opcode) || + TII->isLoad(Opcode) || // TODO: Do loads and stores. + TII->isStore(Opcode)); + } + + /// isLoopInvariantInst - Returns true if the instruction is loop + /// invariant. I.e., all virtual register operands are defined outside of + /// the loop, physical registers aren't accessed (explicitly or implicitly), + /// and the instruction is hoistable. + /// + bool isLoopInvariantInst(MachineInstr &I); + + /// FindPredecessors - Get all of the predecessors of the loop that are not + /// back-edges. + /// + void FindPredecessors(std::vector &Preds){ + const MachineBasicBlock *Header = CurLoop->getHeader(); + + for (MachineBasicBlock::const_pred_iterator + I = Header->pred_begin(), E = Header->pred_end(); I != E; ++I) + if (!CurLoop->contains(*I)) + Preds.push_back(*I); + } + + /// MoveInstToBlock - Moves the machine instruction to the bottom of the + /// predecessor basic block (but before the terminator instructions). + /// + void MoveInstToBlock(MachineBasicBlock *MBB, MachineInstr *MI) { + MachineBasicBlock::iterator Iter = MBB->getFirstTerminator(); + MBB->insert(Iter, MI); + } + + /// HoistRegion - Walk the specified region of the CFG (defined by all + /// blocks dominated by the specified block, and that are in the current + /// loop) in depth first order w.r.t the DominatorTree. This allows us to + /// visit definitions before uses, allowing us to hoist a loop body in one + /// pass without iteration. + /// + void HoistRegion(MachineDomTreeNode *N); + + /// Hoist - When an instruction is found to only use loop invariant operands + /// that is safe to hoist, this instruction is called to do the dirty work. + /// + bool Hoist(MachineInstr &MI); + }; + + char MachineLICM::ID = 0; + RegisterPass X("machine-licm", + "Machine Loop Invariant Code Motion"); +} // end anonymous namespace + +FunctionPass *llvm::createMachineLICMPass() { return new MachineLICM(); } + +/// Hoist expressions out of the specified loop. Note, alias info for inner loop +/// is not preserved so it is not a good idea to run LICM multiple times on one +/// loop. +/// +bool MachineLICM::runOnMachineFunction(MachineFunction &MF) { + if (!PerformLICM) return false; // For debugging. + + Changed = false; + TII = MF.getTarget().getInstrInfo(); + + // Get our Loop information... + LI = &getAnalysis(); + DT = &getAnalysis(); + + for (MachineLoopInfo::iterator + I = LI->begin(), E = LI->end(); I != E; ++I) { + MachineLoop *L = *I; + CurLoop = L; + + // Visit all of the instructions of the loop. We want to visit the subloops + // first, though, so that we can hoist their invariants first into their + // containing loop before we process that loop. + SmallVector Loops; + GatherAllLoops(L, Loops); + + for (SmallVector::iterator + II = Loops.begin(), IE = Loops.end(); II != IE; ++II) { + L = *II; + + // Traverse the body of the loop in depth first order on the dominator + // tree so that we are guaranteed to see definitions before we see uses. + HoistRegion(DT->getNode(L->getHeader())); + } + } + + return Changed; +} + +/// MapVirtualRegisterDefs - Create a map of which machine instruction defines a +/// virtual register. +/// +void MachineLICM::MapVirtualRegisterDefs(const MachineFunction &MF) { + for (MachineFunction::const_iterator + I = MF.begin(), E = MF.end(); I != E; ++I) { + const MachineBasicBlock &MBB = *I; + + for (MachineBasicBlock::const_iterator + II = MBB.begin(), IE = MBB.end(); II != IE; ++II) { + const MachineInstr &MI = *II; + + if (MI.getNumOperands() > 0) { + const MachineOperand &MO = MI.getOperand(0); + + if (MO.isRegister() && MO.isDef() && + MRegisterInfo::isVirtualRegister(MO.getReg())) + VRegDefs[MO.getReg()] = &MI; + } + } + } +} + +/// HoistRegion - Walk the specified region of the CFG (defined by all blocks +/// dominated by the specified block, and that are in the current loop) in depth +/// first order w.r.t the DominatorTree. This allows us to visit definitions +/// before uses, allowing us to hoist a loop body in one pass without iteration. +/// +void MachineLICM::HoistRegion(MachineDomTreeNode *N) { + assert(N != 0 && "Null dominator tree node?"); + MachineBasicBlock *BB = N->getBlock(); + + // If this subregion is not in the top level loop at all, exit. + if (!CurLoop->contains(BB)) return; + + // Only need to process the contents of this block if it is not part of a + // subloop (which would already have been processed). + if (!isInSubLoop(BB)) + for (MachineBasicBlock::iterator + I = BB->begin(), E = BB->end(); I != E; ) { + MachineInstr &MI = *I++; + + // Try hoisting the instruction out of the loop. We can only do this if + // all of the operands of the instruction are loop invariant and if it is + // safe to hoist the instruction. + if (Hoist(MI)) + // Hoisting was successful! Remove bothersome instruction now. + MI.getParent()->remove(&MI); + } + + const std::vector &Children = N->getChildren(); + + for (unsigned I = 0, E = Children.size(); I != E; ++I) + HoistRegion(Children[I]); +} + +/// isLoopInvariantInst - Returns true if the instruction is loop +/// invariant. I.e., all virtual register operands are defined outside of the +/// loop, physical registers aren't accessed (explicitly or implicitly), and the +/// instruction is hoistable. +/// +bool MachineLICM::isLoopInvariantInst(MachineInstr &I) { + const TargetInstrDescriptor *TID = I.getInstrDescriptor(); + + // Don't hoist if this instruction implicitly reads physical registers or + // doesn't take any operands. + if (TID->ImplicitUses || !I.getNumOperands()) return false; + + if (!CanHoistInst(I)) return false; + + // The instruction is loop invariant if all of its operands are loop-invariant + for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = I.getOperand(i); + + if (!MO.isRegister() || !MO.isUse()) + continue; + + unsigned Reg = MO.getReg(); + + // Don't hoist instructions that access physical registers. + if (!MRegisterInfo::isVirtualRegister(Reg)) + return false; + + assert(VRegDefs[Reg] && "Machine instr not mapped for this vreg?!"); + + // If the loop contains the definition of an operand, then the instruction + // isn't loop invariant. + if (CurLoop->contains(VRegDefs[Reg]->getParent())) + return false; + } + + // If we got this far, the instruction is loop invariant! + return true; +} + +/// Hoist - When an instruction is found to only use loop invariant operands +/// that is safe to hoist, this instruction is called to do the dirty work. +/// +bool MachineLICM::Hoist(MachineInstr &MI) { + if (!isLoopInvariantInst(MI)) return false; + + std::vector Preds; + + // Non-back-edge predecessors. + FindPredecessors(Preds); + if (Preds.empty()) return false; + + // Check that the predecessors are qualified to take the hoisted + // instruction. I.e., there is only one edge from each predecessor, and it's + // to the loop header. + for (std::vector::iterator + I = Preds.begin(), E = Preds.end(); I != E; ++I) { + MachineBasicBlock *MBB = *I; + + // FIXME: We are assuming at first that the basic blocks coming into this + // loop have only one successor each. This isn't the case in general because + // we haven't broken critical edges or added preheaders. + if (MBB->succ_size() != 1) return false; + assert(*MBB->succ_begin() == CurLoop->getHeader() && + "The predecessor doesn't feed directly into the loop header!"); + } + + // Now move the instructions to the predecessors. + for (std::vector::iterator + I = Preds.begin(), E = Preds.end(); I != E; ++I) + MoveInstToBlock(*I, MI.clone()); + + Changed = true; + return true; +} diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index e1ded3639453..6a53a7631517 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -684,12 +684,15 @@ def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "subfic $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; -def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), - "li $rD, $imm", IntGeneral, - [(set GPRC:$rD, immSExt16:$imm)]>; -def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), - "lis $rD, $imm", IntGeneral, - [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; + +let isReMaterializable = 1 in { + def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), + "li $rD, $imm", IntGeneral, + [(set GPRC:$rD, immSExt16:$imm)]>; + def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), + "lis $rD, $imm", IntGeneral, + [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; +} } let PPC970_Unit = 1 in { // FXU Operations.