Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.

llvm-svn: 26445
This commit is contained in:
Chris Lattner 2006-03-01 04:57:39 +00:00
parent 21d44e6dfe
commit f418435819
3 changed files with 42 additions and 25 deletions

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@ -185,6 +185,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setSetCCResultContents(ZeroOrOneSetCCResult);
setStackPointerRegisterToSaveRestore(PPC::R1);
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::SINT_TO_FP);
computeRegisterProperties();
}
@ -997,6 +1000,43 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
return BB;
}
SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
TargetMachine &TM = getTargetMachine();
SelectionDAG &DAG = DCI.DAG;
switch (N->getOpcode()) {
default: break;
case ISD::SINT_TO_FP:
if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
// Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
// We allow the src/dst to be either f32/f64, but force the intermediate
// type to be i64.
if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT &&
N->getOperand(0).getValueType() == MVT::i64) {
SDOperand Val = N->getOperand(0).getOperand(0);
if (Val.getValueType() == MVT::f32) {
Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
DCI.AddToWorklist(Val.Val);
}
Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
DCI.AddToWorklist(Val.Val);
Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
DCI.AddToWorklist(Val.Val);
if (N->getValueType(0) == MVT::f32) {
Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
DCI.AddToWorklist(Val.Val);
}
return Val;
}
}
break;
}
return SDOperand();
}
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
PPCTargetLowering::ConstraintType

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@ -81,6 +81,8 @@ namespace llvm {
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vector<SDOperand>

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@ -328,31 +328,6 @@ computable using the spiffy altivec instructions.
Compile this:
double %test(double %X) {
%Y = cast double %X to long
%Z = cast long %Y to double
ret double %Z
}
to this:
_test:
fctidz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
lwz r3, -8(r1)
stw r2, -12(r1)
stw r3, -16(r1)
lfd f0, -16(r1)
fcfid f1, f0
blr
without the lwz/stw's.
===-------------------------------------------------------------------------===
Compile this:
int foo(int a) {
int b = (a < 8);
if (b) {